ICache now returns the "next PC" signal.
useful for other modules that need access to the fetch PC on the cycle it is sent to the SRAM.
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@ -26,7 +26,7 @@ class FrontendResp extends CoreBundle {
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val xcpt_if = Bool()
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}
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class CPUFrontendIO extends Bundle {
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class CPUFrontendIO extends CoreBundle {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp).flip
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@ -34,6 +34,7 @@ class CPUFrontendIO extends Bundle {
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val invalidate = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBits+1)
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}
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class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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@ -102,6 +103,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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icache.io.mem <> io.mem
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icache.io.req.valid := !stall && !s0_same_block
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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