riscv/rocket-chip
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fix rocc exception/s bit

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This commit is contained in:
Yunsup Lee 2015-03-17 05:08:19 -07:00
parent 66388be1ce
commit 5b4653b621
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/ctrl.scala
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@ -667,6 +667,6 @@ class Control extends CoreModule
io.dmem.sret := wb_xcpt // obviously not an sret, but sufficient
io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_xcpt && io.dpath.status.xs != 0
io.rocc.s := io.dpath.status.prv != 0 // should we just pass all of mstatus?
io.rocc.exception := wb_xcpt && io.dpath.status.xs.orR
io.rocc.s := io.dpath.status.prv.orR // should we just pass all of mstatus?
}