Merge pull request #10 from wsong83/fix
L1 D$ writeback unit, reduce re-read data array
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commit
5ed2899e56
@ -409,11 +409,13 @@ class WritebackUnit extends L1HellaCacheModule {
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}
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when (r2_data_req_fired) {
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io.release.valid := beat_done
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when(!io.release.ready) {
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r1_data_req_fired := false
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r2_data_req_fired := false
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data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
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} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 }
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when(beat_done) {
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when(!io.release.ready) {
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r1_data_req_fired := false
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r2_data_req_fired := false
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data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
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} .otherwise { if(refillCyclesPerBeat > 1) buf_v := 0 }
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}
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when(!r1_data_req_fired) {
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// We're done if this is the final data request and the Release can be sent
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active := data_req_cnt < UInt(refillCycles) || !io.release.ready
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@ -880,7 +882,7 @@ class HellaCache extends L1HellaCacheModule {
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val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable
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val s2_recycle_next = Reg(init=Bool(false))
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when (s1_valid || s1_replay) { s2_recycle_next := (s1_valid || s1_replay) && s2_recycle_ecc }
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when (s1_valid || s1_replay) { s2_recycle_next := s2_recycle_ecc }
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s2_recycle := s2_recycle_ecc || s2_recycle_next
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// after a nack, block until nack condition resolves to save energy
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