Merge [shm]call into ecall, [shm]ret into eret
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@ -187,14 +187,12 @@ class CSRFile extends CoreModule
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Mux(io.rw.cmd === CSR.S, io.rw.rdata | io.rw.wdata,
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host_pcr_bits.data)))
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val opcode = io.rw.addr(3,0)
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// The following comparison is meant to be opcode === SFENCE_VM(23,20). But
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// FOR SOME FUCKING REASON, extracting SFENCE_VM(23,20) gives 3, not 4.
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val insn_sfence_vm = opcode === 4 && system_insn && priv_sufficient
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val insn_redirect_trap = opcode === MRTS(23,20) && system_insn && priv_sufficient
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val insn_ret = opcode === SRET(23,20) /* or H/MRET */ && io.rw.addr(1) && system_insn && priv_sufficient
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val insn_break = opcode === SBREAK(23,20) && io.rw.addr(0) && system_insn && priv_sufficient
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val insn_call = opcode === SCALL(23,20) /* or H/MCALL */ && system_insn && priv_sufficient
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val opcode = io.rw.addr
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val insn_call = !opcode(8) && !opcode(0) && system_insn && priv_sufficient
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val insn_break = !opcode(8) && opcode(0) && system_insn && priv_sufficient
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val insn_ret = opcode(8) && !opcode(0) && system_insn && priv_sufficient
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val insn_sfence_vm = opcode(8) && opcode(0) && system_insn && priv_sufficient
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val insn_redirect_trap = opcode(2) && system_insn && priv_sufficient
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val csr_xcpt = (cpu_wen && read_only) ||
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(cpu_ren && (!priv_sufficient || !addr_valid || fp_csr && !io.status.fs.orR)) ||
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@ -228,7 +226,7 @@ class CSRFile extends CoreModule
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when (csr_xcpt) {
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reg_mcause := Causes.illegal_instruction
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when (insn_break) { reg_mcause := Causes.breakpoint }
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when (insn_call) { reg_mcause := Causes.scall + csr_addr_priv }
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when (insn_call) { reg_mcause := Causes.ecall }
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}
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reg_mbadaddr := io.pc
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@ -216,8 +216,6 @@ object XDecode extends DecodeConstants
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SCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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SBREAK-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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SRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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HCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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MRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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MRTS-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
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CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.W,N,N,N),
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CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.S,N,N,N),
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@ -95,12 +95,9 @@ object Instructions {
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def SC_D = Bits("b00011????????????011?????0101111")
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def SCALL = Bits("b00000000000000000000000001110011")
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def SBREAK = Bits("b00000000000100000000000001110011")
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def SRET = Bits("b00010000001000000000000001110011")
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def SFENCE_VM = Bits("b000100000100?????000000001110011")
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def HCALL = Bits("b00010000000000000000000001110011")
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def MCALL = Bits("b00100000000000000000000001110011")
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def MRET = Bits("b00110000001000000000000001110011")
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def MRTS = Bits("b00110000100100000000000001110011")
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def SRET = Bits("b00010000000000000000000001110011")
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def SFENCE_VM = Bits("b000100000001?????000000001110011")
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def MRTS = Bits("b00110000010100000000000001110011")
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def CSRRW = Bits("b?????????????????001?????1110011")
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def CSRRS = Bits("b?????????????????010?????1110011")
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def CSRRC = Bits("b?????????????????011?????1110011")
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@ -198,27 +195,23 @@ object Causes {
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val misaligned_fetch = 0x0
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val fault_fetch = 0x1
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val illegal_instruction = 0x2
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val scall = 0x4
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val hcall = 0x5
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val mcall = 0x6
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val breakpoint = 0x7
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val misaligned_load = 0x8
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val fault_load = 0x9
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val misaligned_store = 0xa
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val fault_store = 0xb
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val misaligned_load = 0x4
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val fault_load = 0x5
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val misaligned_store = 0x6
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val fault_store = 0x7
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val ecall = 0x8
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val breakpoint = 0x9
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val all = {
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val res = collection.mutable.ArrayBuffer[Int]()
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res += misaligned_fetch
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res += fault_fetch
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res += illegal_instruction
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res += scall
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res += hcall
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res += mcall
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res += breakpoint
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res += misaligned_load
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res += fault_load
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res += misaligned_store
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res += fault_store
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res += ecall
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res += breakpoint
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res.toArray
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}
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}
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