fix long-standing dcache bug
have to initialize register, if it is used the same cycle it is begin written
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5b4653b621
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@ -628,7 +628,7 @@ class HellaCache extends L1HellaCacheModule {
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val s3_req = Reg(io.cpu.req.bits.clone)
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val s3_way = Reg(Bits())
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val s1_recycled = RegEnable(s2_recycle, s1_clk_en)
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val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)
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val s1_read = isRead(s1_req.cmd)
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val s1_write = isWrite(s1_req.cmd)
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val s1_sc = s1_req.cmd === M_XSC
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