Andrew Waterman
a3061047e3
Instantiate blocking D$ when NMSHRS=0
2016-05-24 15:05:41 -07:00
Andrew Waterman
9dd23a603a
Remove HTIF port
2016-05-03 13:41:58 -07:00
Andrew Waterman
f784f4da93
Rename PRCICoreIO to PRCITileIO
2016-05-02 18:08:01 -07:00
Andrew Waterman
83fa489cef
Stop using HTIF CSR port
...
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
Andrew Waterman
fb5c38c186
Handle invalidate_lr in cache arbiter, not tile
2016-04-27 11:22:04 -07:00
Andrew Waterman
e652821962
Use correct kind of TileLink arbiter
...
It was "correct" before, but broke Chisel3 build.
2016-03-28 22:53:47 -07:00
Andrew Waterman
a4685a073f
Don't instantiate PTW when UseVM=false
2016-03-25 14:17:25 -07:00
Andrew Waterman
27b3cca046
Discover D$, PTW port counts dynamically
...
This is a generator, after all...
2016-03-25 14:16:56 -07:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Yunsup Lee
15ac4d317f
RoCC PTW refactoring
2016-02-25 17:15:38 -08:00
Howard Mao
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
Howard Mao
304d8b814a
Implement client-side DMA controller
2015-12-16 21:24:24 -08:00
Howard Mao
369ee74a2c
change names of RoCC tilelink interfaces to be more sensible
2015-12-02 16:28:23 -08:00
Howard Mao
73b0263663
disconnect fpu port if no fpu-using RoCC accelerators
2015-12-01 20:41:58 -08:00
Howard Mao
dcca0b1d86
fix up FPU connection
2015-12-01 18:14:58 -08:00
Howard Mao
08f77ca90d
Merge branch 'master' into rocc-fpu-port
2015-12-01 18:00:28 -08:00
Howard Mao
e76dfa55f7
change the way rocc is parameterized
2015-12-01 17:54:56 -08:00
Howard Mao
4833d41dbc
make the connection of FPU ports optional per accelerator
2015-12-01 16:48:05 -08:00
Howard Mao
0b15b19381
add arbiter for FPU
2015-12-01 10:22:31 -08:00
Howard Mao
9256239206
implement support for multiple RoCC accelerators
2015-11-26 12:46:01 -08:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Henry Cook
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
Henry Cook
969ecaecf8
pass parameters to BuildRoCC
2015-10-14 14:16:47 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Andrew Waterman
52fc34a138
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
Andrew Waterman
cc447c8110
Refactor pipeline RTL (merge ctrl + dpath into rocket)
2015-07-21 17:10:56 -07:00
Henry Cook
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
Henry Cook
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
Christopher Celio
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
Yunsup Lee
ebbd14254c
uncached port should be a HeaderlessUncachedTileLinkIO type
2015-03-13 02:12:23 -07:00
Henry Cook
51e4cd7616
Added UncachedTileLinkIO port to RocketTile, simplify arbitration
2015-03-12 16:30:04 -07:00
Henry Cook
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
Henry Cook
b36d751250
sret bugfix: bypass arbiter
2015-03-05 13:14:16 -08:00
Christopher Celio
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
Henry Cook
c9320862ae
add l2 dmem signal to rocc
2014-12-12 16:55:08 -08:00
Adam Izraelevitz
3e256439c9
Add abstract class Tile
2014-09-24 13:04:20 -07:00
Yunsup Lee
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
Henry Cook
5eb5e9eaf5
Standardize ()=>Module(...) top-level Parameters
2014-09-07 17:54:41 -07:00
Henry Cook
b42a2ab40a
Final parameter refactor
2014-09-01 13:28:58 -07:00
Henry Cook
2de268b3b1
Cache utility traits. Completely compiles, asm tests hang.
2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
Adam Izraelevitz
812353bace
Ported FPU parameters to new Chisel Parameters
2014-08-19 11:37:27 -07:00
Andrew Waterman
04593d433e
clean up Int <-> Boolean conversion stuff
2014-06-14 13:58:07 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Andrew Waterman
c7110c8389
Make FPU pipeline depths configurable
2014-02-28 13:39:59 -08:00
Yunsup Lee
97b1841fcf
change dcache tag bits to 7
2014-02-22 22:53:04 -08:00
Stephen Twigg
6a02d15c21
Merge branch 'master' into hwacha-port
2014-02-04 17:05:03 -08:00
