change names of RoCC tilelink interfaces to be more sensible
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@ -42,8 +42,8 @@ class RoCCInterface(implicit p: Parameters) extends Bundle {
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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val imem = new ClientUncachedTileLinkIO
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val dmem = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
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val autl = new ClientUncachedTileLinkIO
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val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
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val iptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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@ -122,10 +122,8 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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io.mem.req.bits.data := Bits(0) // we're not performing any stores...
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io.mem.invalidate_lr := false
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io.imem.acquire.valid := false
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io.imem.grant.ready := false
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io.dmem.head.acquire.valid := false
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io.dmem.head.grant.ready := false
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io.autl.acquire.valid := false
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io.autl.grant.ready := false
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io.iptw.req.valid := false
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io.dptw.req.valid := false
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io.pptw.req.valid := false
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@ -172,10 +170,8 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.dmem.head.acquire.valid := Bool(false)
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io.dmem.head.grant.ready := Bool(false)
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io.imem.acquire.valid := Bool(false)
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io.imem.grant.ready := Bool(false)
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io.autl.acquire.valid := Bool(false)
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io.autl.grant.ready := Bool(false)
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io.iptw.req.valid := Bool(false)
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io.pptw.req.valid := Bool(false)
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}
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@ -197,7 +193,7 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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val gnt = io.dmem.head.grant.bits
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val gnt = io.autl.grant.bits
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val recv_data = Reg(UInt(width = tlDataBits))
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val recv_beat = Reg(UInt(width = tlBeatAddrBits))
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@ -218,9 +214,9 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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io.resp.valid := (state === s_resp)
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io.resp.bits.rd := resp_rd
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io.resp.bits.data := count
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io.dmem.head.acquire.valid := (state === s_acq)
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io.dmem.head.acquire.bits := GetBlock(addr_block = addr_block)
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io.dmem.head.grant.ready := (state === s_gnt)
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io.autl.acquire.valid := (state === s_acq)
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io.autl.acquire.bits := GetBlock(addr_block = addr_block)
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io.autl.grant.ready := (state === s_gnt)
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when (io.cmd.fire()) {
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addr := io.cmd.bits.rs1
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@ -231,9 +227,9 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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state := s_acq
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}
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when (io.dmem.head.acquire.fire()) { state := s_gnt }
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when (io.autl.acquire.fire()) { state := s_gnt }
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when (io.dmem.head.grant.fire()) {
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when (io.autl.grant.fire()) {
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recv_beat := gnt.addr_beat
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recv_data := gnt.data
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state := s_check
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@ -257,8 +253,6 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.imem.acquire.valid := Bool(false)
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io.imem.grant.ready := Bool(false)
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io.dptw.req.valid := Bool(false)
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io.iptw.req.valid := Bool(false)
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io.pptw.req.valid := Bool(false)
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@ -13,7 +13,7 @@ case object BuildRoCC extends Field[Seq[RoccParameters]]
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case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 1,
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nMemChannels: Int = 0,
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useFPU: Boolean = false)
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abstract class Tile(resetSignal: Bool = null)
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@ -63,8 +63,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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// If so specified, build an RoCC module and wire it to core + TileLink ports,
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// otherwise just hookup the icache
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io.uncached <> (if (usingRocc) {
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val iMemArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
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iMemArb.io.in(0) <> icache.io.mem
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val uncachedArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
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uncachedArb.io.in(0) <> icache.io.mem
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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core.io.rocc.resp <> respArb.io.out
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@ -82,7 +82,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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rocc.io.exception := core.io.rocc.exception
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dcIF.io.requestor <> rocc.io.mem
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dcArb.io.requestor(2 + i) <> dcIF.io.cache
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iMemArb.io.in(1 + i) <> rocc.io.imem
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uncachedArb.io.in(1 + i) <> rocc.io.autl
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ptw.io.requestor(2 + 3 * i) <> rocc.io.iptw
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ptw.io.requestor(3 + 3 * i) <> rocc.io.dptw
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ptw.io.requestor(4 + 3 * i) <> rocc.io.pptw
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@ -108,7 +108,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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roccs.flatMap(_.io.dmem) :+ iMemArb.io.out
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roccs.flatMap(_.io.utl) :+ uncachedArb.io.out
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} else { Seq(icache.io.mem) })
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if (!usingRocc || nFPUPorts == 0) {
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