make the connection of FPU ports optional per accelerator
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0b15b19381
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4833d41dbc
@ -11,6 +11,7 @@ case object CoreName extends Field[String]
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case object BuildRoCC extends Field[Seq[Parameters => RoCC]]
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case object RoccOpcodes extends Field[Seq[OpcodeSet]]
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case object RoccAcceleratorMemChannels extends Field[Seq[Int]]
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case object RoccUseFPU extends Field[Seq[Boolean]]
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abstract class Tile(resetSignal: Bool = null)
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(implicit p: Parameters) extends Module(_reset = resetSignal) {
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@ -19,6 +20,8 @@ abstract class Tile(resetSignal: Bool = null)
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val roccMemChannels = p(RoccAcceleratorMemChannels)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val roccUseFPU = p(RoccUseFPU)
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val nFPUPorts = roccUseFPU.filter(useFPU => useFPU).size
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val nDCachePorts = 2 + nRocc
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val nPTWPorts = 2 + 3 * nRocc
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val nCachedTileLinkPorts = 1
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@ -86,15 +89,20 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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rocc
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}
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nRocc))
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fpArb.io.in_req <> roccs.map(_.io.fpu_req)
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roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp
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if (nFPUPorts > 0) {
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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val fp_roccs = roccs.zip(roccUseFPU)
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.filter { case (_, useFPU) => useFPU }
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.map { case (rocc, _) => rocc }
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fpArb.io.in_req <> fp_roccs.map(_.io.fpu_req)
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fp_roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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}
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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