83 lines
3.1 KiB
Scala
83 lines
3.1 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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case object NDCachePorts extends Field[Int]
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case object NTilePorts extends Field[Int]
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case object BuildRoCC extends Field[Option[() => RoCC]]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object DcacheReqTagBits extends Field[Int]
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case object XprLen extends Field[Int]
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case object NXpr extends Field[Int]
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case object NXprBits extends Field[Int]
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case object RocketDCacheParams extends Field[PF]
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case object RocketFrontendParams extends Field[PF]
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class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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if(params(FastLoadByte)) require(params(FastLoadWord))
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require(params(RetireWidth) == 1) // for now...
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO
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}
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// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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val optionalRoCC = params(BuildRoCC)
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val p = params.alter(params(CoreBTBParams)).alter(params(RocketFrontendParams)) // Used in icache, Core
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val icache = Module(new Frontend)(p) //TODO PARAMS: best way to alter both?
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params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core
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val dcache = Module(new HellaCache)
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val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5))
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// 2 ports, 1 from I$, 1 from D$, maybe 3 from RoCC
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val core = Module(new Core)
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val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
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dcArb.io.requestor(0) <> ptw.io.mem
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dcArb.io.requestor(1) <> core.io.dmem
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dcArb.io.mem <> dcache.io.cpu
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ptw.io.requestor(0) <> icache.io.cpu.ptw
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ptw.io.requestor(1) <> dcache.io.cpu.ptw
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core.io.host <> io.host
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core.io.imem <> icache.io.cpu
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core.io.ptw <> ptw.io.dpath
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val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
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val dcPortId = 0
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memArb.io.in(dcPortId) <> dcache.io.mem
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memArb.io.in(1) <> icache.io.mem
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if(!optionalRoCC.isEmpty) {
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val rocc = Module(optionalRoCC.get())
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val dcIF = Module(new SimpleHellaCacheIF)
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dcIF.io.requestor <> rocc.io.mem
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core.io.rocc <> rocc.io
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> rocc.io.imem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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io.tilelink.acquire <> memArb.io.out.acquire
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io.tilelink.grant <> memArb.io.out.grant
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io.tilelink.finish <> memArb.io.out.finish
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// Probes and releases routed directly to coherent dcache
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io.tilelink.probe <> dcache.io.mem.probe
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// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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io.tilelink.release.valid := dcache.io.mem.release.valid
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dcache.io.mem.release.ready := io.tilelink.release.ready
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io.tilelink.release.bits := dcache.io.mem.release.bits
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io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts))))
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}
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