Ported FPU parameters to new Chisel Parameters

rocket/src/main/scala/core.scala

@@ -4,6 +4,9 @@ import Chisel._
 import Util._
 import uncore.HTIFIO
 
+case object FPUParams extends Field[PF]
+case object HasFPU extends Field[Boolean]
+
 class RocketIO(implicit conf: RocketConfiguration) extends Bundle
 {
   val host = new HTIFIO(conf.tl.ln.nClients)
@@ -20,8 +23,8 @@ class Core(implicit conf: RocketConfiguration) extends Module
   val ctrl  = Module(new Control)
   val dpath = Module(new Datapath)
 
-  if (!conf.fpu.isEmpty) {
-    val fpu = Module(new FPU(conf.fpu.get))
+  if (!params(HasFPU)) {
+    val fpu = Module(new FPU,params(FPUParams))
     dpath.io.fpu <> fpu.io.dpath
     ctrl.io.fpu <> fpu.io.ctrl
   }

rocket/src/main/scala/csr.scala

@@ -164,9 +164,9 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
   val read_ptbr = reg_ptbr(conf.as.paddrBits-1, conf.as.pgIdxBits) << conf.as.pgIdxBits
 
   val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
-    CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)),
-    CSRs.frm -> (if (!conf.fpu.isEmpty) reg_frm else UInt(0)),
-    CSRs.fcsr -> (if (!conf.fpu.isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
+    CSRs.fflags -> (if (!params(HasFPU)) reg_fflags else UInt(0)),
+    CSRs.frm -> (if (!params(HasFPU)) reg_frm else UInt(0)),
+    CSRs.fcsr -> (if (!params(HasFPU)) Cat(reg_frm, reg_fflags) else UInt(0)),
     CSRs.cycle -> reg_time,
     CSRs.time -> reg_time,
     CSRs.instret -> reg_instret,
@@ -208,7 +208,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
       reg_status.zero := 0
       if (!conf.vm) reg_status.vm := false
       if (conf.rocc.isEmpty) reg_status.er := false
-      if (conf.fpu.isEmpty) reg_status.ef := false
+      if (params(HasFPU)) reg_status.ef := false
     }
     when (decoded_addr(CSRs.fflags))   { reg_fflags := wdata }
     when (decoded_addr(CSRs.frm))      { reg_frm := wdata }

rocket/src/main/scala/ctrl.scala

@@ -316,7 +316,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   }
 
   var decode_table = XDecode.table
-  if (!conf.fpu.isEmpty) decode_table ++= FDecode.table
+  if (!params(HasFPU)) decode_table ++= FDecode.table
   if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
 
   val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
@@ -411,13 +411,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
 
   val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil
   val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
-  if (conf.fpu.isEmpty)
+  if (params(HasFPU))
     legal_csrs --= fp_csrs
 
   val id_csr_addr = io.dpath.inst(31,20)
   val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i))
   val id_csr_en = id_csr != CSR.N
-  val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
+  val id_csr_fp = Bool(!params(HasFPU)) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
   val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
   val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr)
   val id_csr_privileged = id_csr_en &&
@@ -623,7 +623,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   val sboard = new Scoreboard(32)
   sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
 
-  val id_stall_fpu = if (!conf.fpu.isEmpty) {
+  val id_stall_fpu = if (!params(HasFPU)) {
     val fp_sboard = new Scoreboard(32)
     fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr)
     fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)

rocket/src/main/scala/fpu.scala

@@ -6,7 +6,8 @@ import Util._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
 
-case class FPUConfig(sfmaLatency: Int = 2, dfmaLatency: Int = 3)
+case object SFMALatency
+case object DFMALatency
 
 object FPConstants
 {
@@ -340,7 +341,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
   io.out := Pipe(valid, res, latency-1)
 }
 
-class FPU(conf: FPUConfig) extends Module
+class FPU extends Module
 {
   val io = new Bundle {
     val ctrl = (new CtrlFPUIO).flip
@@ -396,11 +397,11 @@ class FPU(conf: FPUConfig) extends Module
   req.in3 := ex_rs3
   req.typ := ex_reg_inst(21,20)
 
-  val sfma = Module(new FPUFMAPipe(conf.sfmaLatency, 23, 9))
+  val sfma = Module(new FPUFMAPipe(params(SFMALatency), 23, 9))
   sfma.io.in.valid := ex_reg_valid && ex_ctrl.fma && ex_ctrl.single
   sfma.io.in.bits := req
 
-  val dfma = Module(new FPUFMAPipe(conf.dfmaLatency, 52, 12))
+  val dfma = Module(new FPUFMAPipe(params(DFMALatency), 52, 12))
   dfma.io.in.valid := ex_reg_valid && ex_ctrl.fma && !ex_ctrl.single
   dfma.io.in.bits := req
 

rocket/src/main/scala/tile.scala

@@ -6,7 +6,6 @@ import Util._
 
 case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
                                icache: ICacheConfig, dcache: DCacheConfig,
-                               fpu: Option[FPUConfig] = None,
                                rocc: Option[RocketConfiguration => RoCC] = None,
                                retireWidth: Int = 1,
                                vm: Boolean = true,