add arbiter for FPU
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1db2da00f3
commit
0b15b19381
@ -5,6 +5,7 @@ package rocket
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import Chisel._
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import uncore._
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import cde.{Parameters, Field}
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import junctions.ParameterizedBundle
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class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
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{
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@ -53,3 +54,51 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
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io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> log2Up(n)
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}
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}
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class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)
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(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val in_req = Vec(n, Decoupled(reqTyp)).flip
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val in_resp = Vec(n, Decoupled(respTyp))
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val out_req = Decoupled(reqTyp)
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val out_resp = Decoupled(respTyp).flip
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}
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if (n > 1) {
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val route_q = Module(new Queue(UInt(width = log2Up(n)), 2))
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val req_arb = Module(new RRArbiter(reqTyp, n))
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req_arb.io.in <> io.in_req
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val req_helper = DecoupledHelper(
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req_arb.io.out.valid,
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route_q.io.enq.ready,
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io.out_req.ready)
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io.out_req.bits := req_arb.io.out.bits
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io.out_req.valid := req_helper.fire(io.out_req.ready)
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route_q.io.enq.bits := req_arb.io.chosen
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route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready)
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req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid)
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val resp_sel = route_q.io.deq.bits
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val resp_ready = io.in_resp(resp_sel).ready
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val resp_helper = DecoupledHelper(
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resp_ready,
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route_q.io.deq.valid,
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io.out_resp.valid)
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val resp_valid = resp_helper.fire(resp_ready)
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for (i <- 0 until n) {
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io.in_resp(i).bits := io.out_resp.bits
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io.in_resp(i).valid := resp_valid && resp_sel === UInt(i)
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}
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route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid)
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io.out_resp.ready := resp_helper.fire(io.out_resp.valid)
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} else {
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io.out_req <> io.in_req.head
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io.in_resp.head <> io.out_resp
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}
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}
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@ -537,13 +537,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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io.rocc.cmd.bits.rs1 := wb_reg_wdata
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io.rocc.cmd.bits.rs2 := wb_reg_rs2
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if (usingFPU && usingRoCC) {
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io.fpu.cp_req <> io.rocc.fpu_req
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io.fpu.cp_resp <> io.rocc.fpu_resp
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} else {
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io.fpu.cp_req.valid := Bool(false)
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}
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if (enableCommitLog) {
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val pc = Wire(SInt(width=64))
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pc := wb_reg_pc
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@ -52,8 +52,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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icache.io.cpu <> core.io.imem
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core.io.ptw <> ptw.io.dpath
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//If so specified, build an FPU module and wire it in
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if (p(UseFPU)) core.io.fpu <> Module(new FPU()(p)).io
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val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
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fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
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// Connect the caches and ROCC to the outer memory system
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io.cached.head <> dcache.io.mem
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@ -86,6 +86,16 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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rocc
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}
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nRocc))
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fpArb.io.in_req <> roccs.map(_.io.fpu_req)
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roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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