Merge branch 'master' into rocc-fpu-port
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commit
08f77ca90d
@ -8,16 +8,16 @@ import Util._
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import cde.{Parameters, Field}
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case object CoreName extends Field[String]
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case object BuildRoCC extends Field[Seq[Parameters => RoCC]]
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case object RoccOpcodes extends Field[Seq[OpcodeSet]]
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case object RoccAcceleratorMemChannels extends Field[Seq[Int]]
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case object RoccUseFPU extends Field[Seq[Boolean]]
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case object BuildRoCC extends Field[Seq[RoccParameters]]
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case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 1)
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abstract class Tile(resetSignal: Bool = null)
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(implicit p: Parameters) extends Module(_reset = resetSignal) {
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val buildRocc = p(BuildRoCC)
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val roccOpcodes = p(RoccOpcodes)
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val roccMemChannels = p(RoccAcceleratorMemChannels)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val roccUseFPU = p(RoccUseFPU)
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@ -69,13 +69,14 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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core.io.rocc.resp <> respArb.io.out
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val roccOpcodes = buildRocc.map(_.opcodes)
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> core.io.rocc.cmd
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val roccs = buildRocc.zip(roccMemChannels).zipWithIndex.map {
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case ((buildItHere, nchannels), i) =>
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val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels})
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val rocc = buildItHere(accelParams)
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val roccs = buildRocc.zipWithIndex.map {
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case (RoccParameters(_, generator, nchannels), i) =>
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val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels })
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val rocc = generator(accelParams)
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val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.s := core.io.rocc.s
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