RoCC PTW refactoring

rocket/src/main/scala/dma.scala

@@ -350,8 +350,6 @@ class DmaCtrlRegFile(implicit val p: Parameters) extends Module
 class DmaController(implicit p: Parameters) extends RoCC()(p)
     with HasClientDmaParameters {
   io.mem.req.valid := Bool(false)
-  io.iptw.req.valid := Bool(false)
-  io.pptw.req.valid := Bool(false)
   io.resp.valid := Bool(false)
   io.interrupt := Bool(false)
 
@@ -373,7 +371,7 @@ class DmaController(implicit p: Parameters) extends RoCC()(p)
   io.csr.rdata(RESP_STATUS) := reg_status
 
   val frontend = Module(new DmaFrontend)
-  io.dptw <> frontend.io.ptw
+  io.ptw(0) <> frontend.io.ptw
   io.autl <> frontend.io.mem
   crfile.io.incr_outstanding := frontend.io.incr_outstanding
   frontend.io.host_id := io.host_id

rocket/src/main/scala/rocc.scala

@@ -9,6 +9,7 @@ import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]
+case object RoccNPTWPorts extends Field[Int]
 case object RoccNCSRs extends Field[Int]
 
 class RoCCCSRs(implicit p: Parameters) extends CoreBundle()(p) {
@@ -52,9 +53,7 @@ class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
   // These should be handled differently, eventually
   val autl = new ClientUncachedTileLinkIO
   val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
-  val iptw = new TLBPTWIO
-  val dptw = new TLBPTWIO
-  val pptw = new TLBPTWIO
+  val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
   val fpu_req = Decoupled(new FPInput)
   val fpu_resp = Decoupled(new FPResult).flip
   val exception = Bool(INPUT)
@@ -136,9 +135,6 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
 
   io.autl.acquire.valid := false
   io.autl.grant.ready := false
-  io.iptw.req.valid := false
-  io.dptw.req.valid := false
-  io.pptw.req.valid := false
 }
 
 class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
@@ -160,20 +156,22 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
     state := s_ptw_req
   }
 
-  when (io.dptw.req.fire()) { state := s_ptw_resp }
+  private val ptw = io.ptw(0)
 
-  when (state === s_ptw_resp && io.dptw.resp.valid) {
-    error := io.dptw.resp.bits.error
-    ppn := io.dptw.resp.bits.pte.ppn
+  when (ptw.req.fire()) { state := s_ptw_resp }
+
+  when (state === s_ptw_resp && ptw.resp.valid) {
+    error := ptw.resp.bits.error
+    ppn := ptw.resp.bits.pte.ppn
     state := s_resp
   }
 
   when (io.resp.fire()) { state := s_idle }
 
-  io.dptw.req.valid := (state === s_ptw_req)
-  io.dptw.req.bits.addr := req_vpn
-  io.dptw.req.bits.store := Bool(false)
-  io.dptw.req.bits.fetch := Bool(false)
+  ptw.req.valid := (state === s_ptw_req)
+  ptw.req.bits.addr := req_vpn
+  ptw.req.bits.store := Bool(false)
+  ptw.req.bits.fetch := Bool(false)
 
   io.resp.valid := (state === s_resp)
   io.resp.bits.rd := req_rd
@@ -184,8 +182,6 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
   io.mem.req.valid := Bool(false)
   io.autl.acquire.valid := Bool(false)
   io.autl.grant.ready := Bool(false)
-  io.iptw.req.valid := Bool(false)
-  io.pptw.req.valid := Bool(false)
 }
 
 class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
@@ -265,9 +261,6 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
   io.busy := (state =/= s_idle)
   io.interrupt := Bool(false)
   io.mem.req.valid := Bool(false)
-  io.dptw.req.valid := Bool(false)
-  io.iptw.req.valid := Bool(false)
-  io.pptw.req.valid := Bool(false)
 }
 
 class OpcodeSet(val opcodes: Seq[UInt]) {

rocket/src/main/scala/tile.scala

@@ -14,6 +14,7 @@ case class RoccParameters(
   opcodes: OpcodeSet,
   generator: Parameters => RoCC,
   nMemChannels: Int = 0,
+  nPTWPorts : Int = 0,
   csrs: Seq[Int] = Nil,
   useFPU: Boolean = false)
 
@@ -24,7 +25,7 @@ abstract class Tile(resetSignal: Bool = null)
   val nRocc = buildRocc.size
   val nFPUPorts = buildRocc.filter(_.useFPU).size
   val nDCachePorts = 2 + nRocc
-  val nPTWPorts = 2 + 3 * nRocc
+  val nPTWPorts = 2 + p(RoccNPTWPorts)
   val nCachedTileLinkPorts = 1
   val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels)
   val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
@@ -78,6 +79,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
     val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
       val rocc = accelParams.generator(p.alterPartial({
         case RoccNMemChannels => accelParams.nMemChannels
+        case RoccNPTWPorts => accelParams.nPTWPorts
         case RoccNCSRs => accelParams.csrs.size
       }))
       val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
@@ -88,9 +90,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       dcIF.io.requestor <> rocc.io.mem
       dcArb.io.requestor(2 + i) <> dcIF.io.cache
       uncachedArb.io.in(1 + i) <> rocc.io.autl
-      ptw.io.requestor(2 + 3 * i) <> rocc.io.iptw
-      ptw.io.requestor(3 + 3 * i) <> rocc.io.dptw
-      ptw.io.requestor(4 + 3 * i) <> rocc.io.pptw
       rocc
     }
 
@@ -109,6 +108,8 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       }
     }
 
+    ptw.io.requestor.drop(2) <> roccs.flatMap(_.io.ptw)
+
     core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
     core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
     respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))