riscv/rocket-chip
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  • e9752f1d72 pipeline host pcr access Andrew Waterman 2012-12-06 14:22:07 -0800
  • 10a6a42a4a make vlsi use dram model by default Andrew Waterman 2012-12-06 03:13:45 -0800
  • 4dda38204f fix d$ reset bug Andrew Waterman 2012-12-06 03:13:22 -0800
  • 290d3d226c fix AMO and store bypass bugs Andrew Waterman 2012-12-06 02:07:52 -0800
  • aae7a67781 fix llc refill/writeback bugs Andrew Waterman 2012-12-06 02:07:03 -0800
  • d911e635d6 simplify c++ memory models; support +dramsim flag Andrew Waterman 2012-12-04 07:04:26 -0800
  • 50e9d952e8 don't initiate llc refill until writeback drains Andrew Waterman 2012-12-04 06:57:53 -0800
  • 4608660f6e torture revealed a couple bugs Andrew Waterman 2012-12-04 05:57:53 -0800
  • 5dfb388f03 update to newest rocket Andrew Waterman 2012-11-27 02:43:31 -0800
  • 90cae54ac4 fix D$ read/write concurrency bug Andrew Waterman 2012-11-27 02:42:27 -0800
  • 9c857b83f0 refactor PCR file Andrew Waterman 2012-11-27 01:28:06 -0800
  • ea7029484e update to latest rocket Andrew Waterman 2012-11-26 20:57:12 -0800
  • 8103676b37 reduce physical address space to 4GB Andrew Waterman 2012-11-26 20:54:56 -0800
  • 64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS Andrew Waterman 2012-11-26 20:38:45 -0800
  • 608f65e716 don't wastefully read 2x the bits from D$ RAMs Andrew Waterman 2012-11-26 20:34:30 -0800
  • 352bb464b5 clock gate X/M and M/W store data registers Andrew Waterman 2012-11-26 20:33:41 -0800
  • 8a6ff5f9aa fix D$ writeback bug Andrew Waterman 2012-11-25 19:46:48 -0800
  • e12af07722 update to newest rocket Andrew Waterman 2012-11-25 04:40:46 -0800
  • de2f28193a get rid of more global constants Andrew Waterman 2012-11-25 04:24:25 -0800
  • c036cdc1ea add option for 2-cycle load-use delay Andrew Waterman 2012-11-24 22:01:08 -0800
  • b514c7b725 clean up I$ parity code Andrew Waterman 2012-11-24 22:00:43 -0800
  • 55082e45c4 add AVec, which automatically infers element type Andrew Waterman 2012-11-24 18:19:28 -0800
  • 9372912a9c update to newest rocket Andrew Waterman 2012-11-20 05:42:44 -0800
  • 6d47d18c2b catch sigterm to gracefully exit (fixes vcd) Andrew Waterman 2012-11-20 05:40:44 -0800
  • 7330deb13a print stack trace if elaboration fails Andrew Waterman 2012-11-20 05:39:48 -0800
  • 56f9b9721d treat prefetches as read requests Andrew Waterman 2012-11-20 05:38:49 -0800
  • 2b26082132 use 1r1w ram for tags; merge tags & permissions Andrew Waterman 2012-11-20 04:09:26 -0800
  • 72f94d1141 fix virtual address sign extension detection Andrew Waterman 2012-11-20 04:06:57 -0800
  • 30038bda8a bypass stores to subsequent loads Andrew Waterman 2012-11-20 01:32:33 -0800
  • 4d73e6e38a revamp vector yet again with new D$ Yunsup Lee 2012-11-18 03:14:22 -0800
  • 6bd4f93f8c pull out prefetch commands from isRead Yunsup Lee 2012-11-18 03:13:17 -0800
  • 395e4e3dd6 andrew'x fix for D$ corner case in writeback->abort->probe Yunsup Lee 2012-11-18 03:11:06 -0800
  • 06eeb90e2a vector unit interfaces to the new D$ Yunsup Lee 2012-11-17 10:52:10 -0800
  • 81d711e892 fix D$ bug; now D$ doesn't respond to prefetches Yunsup Lee 2012-11-17 10:47:55 -0800
  • 7bcf59a18f support continous compilation via "make test" Andrew Waterman 2012-11-17 19:58:18 -0800
  • b58214d7e3 remove more global constants Andrew Waterman 2012-11-17 17:25:43 -0800
  • 29bc361d6c remove global constants; disentangle hwacha a bit Andrew Waterman 2012-11-17 17:24:08 -0800
  • cf05b604b3 upgrade to new rocket; improve vlsi makefiles Andrew Waterman 2012-11-17 07:21:29 -0800
  • 5a7777fe4d clock gate integer datapath more aggressively Andrew Waterman 2012-11-17 06:48:44 -0800
  • cc067026a2 pipeline D$ response -> FPU regfile Andrew Waterman 2012-11-17 06:48:11 -0800
  • e68b039133 fix misc. D$ control bugs Andrew Waterman 2012-11-17 06:47:27 -0800
  • dad7b71062 provide cmd/addr with cache response Andrew Waterman 2012-11-16 21:26:12 -0800
  • cb8ac73045 provide store data with cache response Andrew Waterman 2012-11-16 21:15:13 -0800
  • 9e010beffe fix D$ refill bug Andrew Waterman 2012-11-16 21:05:29 -0800
  • 672e904c86 update to new rocket/uncore Andrew Waterman 2012-11-16 02:41:50 -0800
  • 8dce89703a new D$ with better QoR and AMO pipelining Andrew Waterman 2012-11-16 02:39:33 -0800
  • 3e6dc35809 issue self-probes for uncached read transactions Andrew Waterman 2012-11-16 02:37:56 -0800
  • a90a1790a5 improve tlb qor Andrew Waterman 2012-11-16 01:59:38 -0800
  • ff8c736d94 move icache invalidate out of request bundle Andrew Waterman 2012-11-16 01:55:45 -0800
  • 6d10115b19 fix D$ tag width Andrew Waterman 2012-11-15 16:45:51 -0800
  • 1a91637673 refactored vector queue interface Yunsup Lee 2012-11-07 01:16:02 -0800
  • be1980dd2d refactored vector queue interface Yunsup Lee 2012-11-07 01:15:33 -0800
  • 29d4c0b857 refactored tlb Yunsup Lee 2012-11-06 23:54:14 -0800
  • 8764fe786a refactored vector tlb Yunsup Lee 2012-11-06 23:53:52 -0800
  • 9a02298f6f andrew's fix for tlb lockup Yunsup Lee 2012-11-06 23:52:58 -0800
  • e2afae011a factor out global constants Andrew Waterman 2012-11-06 08:18:40 -0800
  • 4d1ca8ba3a remove more global consts; refactor DTLBs Andrew Waterman 2012-11-06 08:13:44 -0800
  • e76892f758 remove more global constants Andrew Waterman 2012-11-06 02:55:45 -0800
  • c5b93798fb factor out more global constants Andrew Waterman 2012-11-05 23:52:32 -0800
  • 1305372ce7 refactor flush logic Yunsup Lee 2012-11-05 23:01:08 -0800
  • 9844ba1c1d revamp the vector unit with the new frontend Yunsup Lee 2012-11-05 01:44:02 -0800
  • ee081d1671 modify code to fix UFix := Bits error Yunsup Lee 2012-11-04 23:31:58 -0800
  • 2a25307a8f revamp the vector unit with the new frontend Yunsup Lee 2012-11-03 21:51:46 -0700
  • 5b20ed71be move rd=0 check into bypass logic Andrew Waterman 2012-11-05 01:30:57 -0800
  • 5e103054fd fix bug in quine mccluskey Andrew Waterman 2012-11-05 00:28:25 -0800
  • dd6ee2571d add vector vm tests Yunsup Lee 2012-11-04 19:29:47 -0800
  • 0c372fc9ec refactor I$ config into RocketConfiguration Andrew Waterman 2012-11-04 17:00:19 -0800
  • e9eca6a95d refactor I$ config; remove Top class Andrew Waterman 2012-11-04 16:59:36 -0800
  • 4ed2d614a2 update to new rocket; retime fpu in dc-syn Andrew Waterman 2012-11-04 16:43:02 -0800
  • 7380c9fe60 aggressively clock gate int and fp datapaths Andrew Waterman 2012-11-04 16:40:14 -0800
  • bd2d61de03 use 8T SRAM for I$; gate clock more aggressively Andrew Waterman 2012-11-04 16:39:25 -0800
  • fedee6c67d add generic error correcting codes Andrew Waterman 2012-10-30 01:03:47 -0700
  • 0cd0f8a9db Initial version of migratory protocol Henry Cook 2012-10-23 18:01:53 -0700
  • 538b23c223 Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles Henry Cook 2012-10-23 12:51:37 -0700
  • 17d2bd8926 Initial version of sbt tasks (elaborate task with no parameters) Henry Cook 2012-10-20 17:27:49 -0700
  • 3edc1f42aa revamp the backup memory link in the vlsi backend Yunsup Lee 2012-10-23 03:31:34 -0700
  • 367b5489d1 first crack at continuous compilation/testing flow Andrew Waterman 2012-10-19 04:09:07 -0700
  • 1ad928cfe2 directly integrate dramsim build Andrew Waterman 2012-10-18 18:59:37 -0700
  • edf0eeed01 integrate updated rocket/uncore Andrew Waterman 2012-10-18 17:51:41 -0700
  • 5773cbb68a rejigger htif to use UncoreConfiguration Andrew Waterman 2012-10-18 17:26:03 -0700
  • 2aecb0024f UncoreConfiguration now contains coherence policy Andrew Waterman 2012-10-18 16:57:28 -0700
  • ffda0e41a9 parameterize width of MemSerdes/MemDesser Andrew Waterman 2012-10-18 16:56:36 -0700
  • e2eb7ce8e9 Cleanup git incompetence Henry Cook 2012-10-16 16:33:07 -0700
  • 88ac5af181 Merged consts-as-traits Henry Cook 2012-10-16 16:32:35 -0700
  • 9df5cfa552 Factored out tilelink classes Henry Cook 2012-10-16 14:26:33 -0700
  • 6cff1c13d8 Refer to traits moved to uncore, add UncoreConfiguration to top Henry Cook 2012-10-16 14:22:23 -0700
  • 8509cda813 Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles Henry Cook 2012-10-16 13:58:18 -0700
  • 6d49dc51a0 Fixed emulator Makefile + extra info in the README file Miquel Moreto 2012-10-16 11:06:48 -0700
  • b9a2af697d turn off HAVE_VEC as it's currently broken Andrew Waterman 2012-10-16 07:38:19 -0700
  • 0a640f2cc6 make DecodeLogic deterministic (hopefully) Andrew Waterman 2012-10-16 04:51:21 -0700
  • 5821900329 don't refetch from I$ if on same 16B block Andrew Waterman 2012-10-11 16:54:28 -0700
  • b955985b38 improve divider QoR Andrew Waterman 2012-10-11 16:50:53 -0700
  • 197154c485 use BTB for JALR Andrew Waterman 2012-10-11 16:50:15 -0700
  • fc648d13a1 remove old Mux1H; add implicit conversions Andrew Waterman 2012-10-11 16:48:51 -0700
  • 661f8e635b merge I$, ITLB, BTB into Frontend Andrew Waterman 2012-10-09 21:35:03 -0700
  • fcd69dba98 add optional early-out to mul/div Andrew Waterman 2012-10-09 18:29:50 -0700
  • 27ddff1adb simplify and improve multiplier Andrew Waterman 2012-10-06 17:32:01 -0700
  • 1418604bf0 new constants organization Henry Cook 2012-10-15 18:52:48 -0700
  • 8970b635b2 improvements to implicit RocketConfiguration parameter Henry Cook 2012-10-15 16:29:49 -0700
  • a7a4e65690 Initial verison of reading config from files Henry Cook 2012-10-15 16:04:25 -0700