riscv/rocket-chip
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revamp the vector unit with the new frontend

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This commit is contained in:
Yunsup Lee 2012-11-03 21:51:46 -07:00
parent 5b20ed71be
commit 2a25307a8f
2 changed files with 7 additions and 6 deletions
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11
rocket/src/main/scala/cpu.scala
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@ -134,15 +134,16 @@ class rocketProc(implicit conf: RocketConfiguration) extends Component
// hooking up vector I$
ptw.io.requestor(2) <> io.vimem.ptw
io.vimem.req.bits.status := dpath.io.ctrl.status
io.vimem.req.bits.pc := vu.io.imem_req.bits.toUFix
io.vimem.req.bits.pc := vu.io.imem_req.bits
io.vimem.req.valid := vu.io.imem_req.valid
io.vimem.req.bits.invalidate := ctrl.io.dpath.flush_inst
io.vimem.req.bits.invalidateTLB := dpath.io.ptbr_wen
vu.io.imem_req.ready := Bool(true)
vu.io.imem_resp.valid := io.vimem.resp.valid
vu.io.imem_resp.bits := io.vimem.resp.bits.data
vu.io.vitlb_exception := io.vimem.resp.bits.xcpt_if
io.vimem.resp.ready := Bool(true)
vu.io.imem_resp.bits.pc := io.vimem.resp.bits.pc
vu.io.imem_resp.bits.data := io.vimem.resp.bits.data
vu.io.imem_resp.bits.xcpt_ma := io.vimem.resp.bits.xcpt_ma
vu.io.imem_resp.bits.xcpt_if := io.vimem.resp.bits.xcpt_if
io.vimem.resp.ready := vu.io.imem_resp.ready
io.vimem.req.bits.mispredict := Bool(false)
io.vimem.req.bits.taken := Bool(false)

2
rocket/src/main/scala/package.scala
View File

@ -18,7 +18,7 @@ object Constants extends
{
def HAVE_RVC = false
def HAVE_FPU = true
def HAVE_VEC = false
def HAVE_VEC = true
val MAX_THREADS =
hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK