riscv/rocket-chip
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pull out prefetch commands from isRead

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Yunsup Lee 2012-11-18 03:13:17 -08:00
parent 3e6dc35809
commit 6bd4f93f8c
1 changed files with 2 additions and 1 deletions
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3
uncore/src/consts.scala
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@ -63,7 +63,8 @@ trait MemoryOpConstants {
val M_XA_MAXU = Bits("b1111", 4);
def isAMO(cmd: Bits) = cmd(3)
def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_PFR || cmd === M_PFW || isAMO(cmd)
def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: Bits) = cmd === M_XRD || isAMO(cmd)
def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
}