riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

revamp the backup memory link in the vlsi backend

Browse Source
This commit is contained in:
Yunsup Lee 2012-10-23 03:31:34 -07:00
parent 367b5489d1
commit 3edc1f42aa
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/main/scala/RocketChip.scala
View File

@ -165,10 +165,10 @@ class ioTop(htif_width: Int) extends Bundle {
val debug = new rocket.ioDebug();
val host = new rocket.ioHost(htif_width);
val mem_backup_en = Bool(INPUT)
val in_mem_rdy = Bool(OUTPUT)
val in_mem_val = Bool(INPUT)
val out_mem_rdy = Bool(INPUT)
val out_mem_val = Bool(OUTPUT)
val in_mem_ready = Bool(OUTPUT)
val in_mem_valid = Bool(INPUT)
val out_mem_ready = Bool(INPUT)
val out_mem_valid = Bool(OUTPUT)
val mem = new uncore.ioMem
}
@ -230,10 +230,10 @@ class Top extends Component {
io.host <> uncore.io.host
uncore.io.mem_backup.resp.valid := io.in_mem_val
uncore.io.mem_backup.resp.valid := io.in_mem_valid
io.out_mem_val := uncore.io.mem_backup.req.valid
uncore.io.mem_backup.req.ready := io.out_mem_rdy
io.out_mem_valid := uncore.io.mem_backup.req.valid
uncore.io.mem_backup.req.ready := io.out_mem_ready
io.mem_backup_en <> uncore.io.mem_backup_en
io.mem <> uncore.io.mem