Initial version of migratory protocol
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Henry Cook
parent
2aecb0024f
commit
0cd0f8a9db
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@ -9,7 +9,7 @@ object cpuCmdToRW {
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR) || (cmd === M_PFW)
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val write = store || amo
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val write = store || amo
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(read, write)
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}
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}
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@ -556,7 +556,7 @@ class MESICoherence extends CoherencePolicyWithUncached {
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: Nil = Enum(8){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactReplyReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactInitReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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def isHit (cmd: Bits, state: UFix): Bool = {
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@ -699,3 +699,173 @@ class MESICoherence extends CoherencePolicyWithUncached {
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(x_type === xactInitWriteUncached)
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}
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}
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class MigratoryCoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: tileSharedByTwo :: tileMigratoryClean :: tileMigratoryDirty :: Nil = Enum(7){ UFix() }
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val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: xactInitReadWordUncached :: xactInitWriteWordUncached :: xactInitAtomicUncached :: xactInitInvalidateOthers :: Nil = Enum(8){ UFix() }
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: xactReplyReadMigratory :: Nil = Enum(9){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: probeReqInvalidateOthers :: Nil = Enum(4){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: probeRepDowngradeDataMigratory :: probeRepDowngradeAckHasCopy :: probeRepInvalidateDataMigratory :: probeRepInvalidateAckMigratory :: Nil = Enum(10){ UFix() }
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactInitReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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def uFixListContains(list: List[UFix], elem: UFix): Bool = list.map(elem === _).reduceLeft(_||_)
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def isHit (cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, uFixListContains(List(tileExclusiveClean, tileExclusiveDirty, tileMigratoryClean, tileMigratoryDirty), state), (state != tileInvalid))
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && messageIsUncached(outstanding)) ||
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(write && (outstanding.x_type != xactInitReadExclusive && outstanding.x_type != xactInitInvalidateOthers))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileExclusiveDirty), Array(
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M_INV -> uFixListContains(List(tileExclusiveDirty,tileMigratoryDirty),state),
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M_CLN -> uFixListContains(List(tileExclusiveDirty,tileMigratoryDirty),state)
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))
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}
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def needsWriteback (state: UFix): Bool = {
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needsTransactionOnCacheControl(M_INV, state)
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, MuxLookup(state, tileExclusiveDirty, Array(
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tileExclusiveClean -> tileExclusiveDirty,
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tileMigratoryClean -> tileMigratoryDirty)), state)
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}
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def newStateOnCacheControl(cmd: Bits) = {
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MuxLookup(cmd, tileInvalid, Array(
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M_INV -> tileInvalid,
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M_CLN -> tileShared
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))
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}
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadShared -> tileShared,
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xactReplyReadExclusive -> MuxLookup(outstanding.x_type, tileExclusiveDirty, Array(
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xactInitReadExclusive -> tileExclusiveDirty,
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xactInitReadShared -> tileExclusiveClean)),
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid,
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xactReplyReadWordUncached -> tileInvalid,
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xactReplyWriteWordUncached -> tileInvalid,
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xactReplyAtomicUncached -> tileInvalid,
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xactReplyReadMigratory -> MuxLookup(outstanding.x_type, tileMigratoryDirty, Array(
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xactInitInvalidateOthers -> tileMigratoryDirty,
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xactInitReadExclusive -> tileMigratoryDirty,
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xactInitReadShared -> tileMigratoryClean))
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeReqInvalidate -> tileInvalid,
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probeReqInvalidateOthers -> tileInvalid,
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probeReqCopy -> state,
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probeReqDowngrade -> MuxLookup(state, tileShared, Array(
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tileExclusiveClean -> tileSharedByTwo,
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tileExclusiveDirty -> tileSharedByTwo,
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tileSharedByTwo -> tileShared,
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tileMigratoryClean -> tileSharedByTwo,
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tileMigratoryDirty -> tileInvalid))
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))
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}
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def getUncachedReadTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadUncached, addr, id)
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def getUncachedWriteTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitWriteUncached, addr, id)
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def getUncachedReadWordTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadWordUncached, addr, id)
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def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits) = TransactionInit(xactInitWriteWordUncached, addr, id, write_mask)
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def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = TransactionInit(xactInitAtomicUncached, addr, id, subword_addr, atomic_op)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, Mux(state === tileInvalid, xactInitReadExclusive, xactInitInvalidateOthers), xactInitReadShared)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, Mux(state === tileInvalid, xactInitReadExclusive, xactInitInvalidateOthers), outstanding.x_type)
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}
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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Assert( incoming.p_type === probeReqInvalidateOthers && needsWriteback(state), "Bad probe request type, should be impossible.")
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val reply = new ProbeReply()
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> Mux(uFixListContains(List(tileExclusiveDirty, tileMigratoryDirty), state),
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probeRepInvalidateDataMigratory, probeRepInvalidateData),
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probeReqDowngrade -> Mux(state === tileMigratoryDirty, probeRepDowngradeDataMigratory, probeRepDowngradeData),
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probeReqCopy -> probeRepCopyData
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))
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val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
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probeReqInvalidate -> Mux(tileExclusiveClean === state, probeRepInvalidateAckMigratory, probeRepInvalidateAck),
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probeReqInvalidateOthers -> Mux(state === tileSharedByTwo, probeRepInvalidateAckMigratory, probeRepInvalidateAck),
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probeReqDowngrade -> Mux(state != tileInvalid, probeRepDowngradeAckHasCopy, probeRepDowngradeAck),
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probeReqCopy -> probeRepCopyAck
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def messageHasData (reply: ProbeReply): Bool = {
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uFixListContains(List(probeRepInvalidateData, probeRepDowngradeData, probeRepCopyData, probeRepInvalidateDataMigratory, probeRepDowngradeDataMigratory), reply.p_type)
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}
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def messageHasData (init: TransactionInit): Bool = uFixListContains(hasDataTypeList, init.x_type)
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def messageHasData (reply: TransactionReply): Bool = {
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uFixListContains(List(xactReplyReadShared, xactReplyReadExclusive, xactReplyReadUncached, xactReplyReadMigratory, xactReplyReadWordUncached, xactReplyAtomicUncached), reply.x_type)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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uFixListContains(List(xactReplyReadShared, xactReplyReadExclusive, xactReplyReadMigratory), reply.x_type)
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}
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def messageIsUncached(init: TransactionInit): Bool = uFixListContains(uncachedTypeList, init.x_type)
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadShared -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive), //TODO: what is count? Depend on probeRep.p_type???
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xactInitReadExclusive -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached,
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xactInitReadWordUncached -> xactReplyReadWordUncached,
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xactInitWriteWordUncached -> xactReplyWriteWordUncached,
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xactInitAtomicUncached -> xactReplyAtomicUncached,
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xactInitInvalidateOthers -> xactReplyReadExclusiveAck //TODO: add this to MESI?
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))
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}
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadShared -> probeReqDowngrade,
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xactInitReadExclusive -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate,
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xactInitReadWordUncached -> probeReqCopy,
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xactInitWriteWordUncached -> probeReqInvalidate,
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xactInitAtomicUncached -> probeReqInvalidate,
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xactInitInvalidateOthers -> probeReqInvalidateOthers
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))
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}
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
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(x_type != xactInitWriteUncached && x_type != xactInitInvalidateOthers)
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}
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached || x_type === xactInitWriteWordUncached || x_type === xactInitAtomicUncached)
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}
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached || x_type === xactInitWriteWordUncached ||x_type === xactInitInvalidateOthers)
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}
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}
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