riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactored vector tlb

Browse Source
This commit is contained in:
Yunsup Lee
2012-11-06 23:53:52 -08:00
parent 9a02298f6f
commit 8764fe786a
3 changed files with 4 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
rocket/src/main/scala/core.scala
View File

@@ -44,18 +44,13 @@ class Core(implicit conf: RocketConfiguration) extends Component
if (HAVE_VEC) {
val vu = new vu()
val vdtlb = new rocketTLB(8)
val vdtlb = new TLB(8)
ptw += vdtlb.io.ptw
vdtlb.io.cpu_req <> vu.io.vec_tlb_req
vu.io.vec_tlb_resp := vdtlb.io.cpu_resp
vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
vdtlb.io <> vu.io.vec_tlb
val pftlb = new rocketTLB(2)
pftlb.io.cpu_req <> vu.io.vec_pftlb_req
val pftlb = new TLB(2)
pftlb.io <> vu.io.vec_pftlb
ptw += pftlb.io.ptw
vu.io.vec_pftlb_resp := pftlb.io.cpu_resp
vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
dpath.io.vec_ctrl <> ctrl.io.vec_dpath

2
rocket/src/main/scala/dpath.scala
View File

@@ -12,7 +12,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val host = new ioHTIF(conf.ntiles)
val ctrl = new ioCtrlDpath().flip
val dmem = new ioHellaCache()(conf.dcache)
val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
val ptw = new IODatapathPTW().flip
val imem = new IOCPUFrontend()(conf.icache)
val fpu = new ioDpathFPU();
@@ -210,7 +209,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.dmem.req.bits.tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6)
io.dtlb.vpn := ex_effective_address >> UFix(PGIDX_BITS)
// processor control regfile read
pcr.io.r.en := io.ctrl.pcr != PCR_N

59
rocket/src/main/scala/tlb.scala
View File

@@ -82,7 +82,6 @@ class TLBResp(entries: Int) extends Bundle
val ppn = UFix(OUTPUT, PPN_BITS)
val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val xcpt_pf = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT)
override def clone = new TLBResp(entries).asInstanceOf[this.type]
@@ -180,61 +179,3 @@ class TLB(entries: Int) extends Component
state := s_ready
}
}
// ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala
// should keep them in sync
class ioDTLB_CPU_req_bundle extends TLBReq
{
val kill = Bool()
val cmd = Bits(width=4) // load/store/amo
}
class ioDTLB_CPU_req extends FIFOIO()( { new ioDTLB_CPU_req_bundle() } )
class ioDTLB_CPU_resp extends TLBResp(1)
class ioDTLB extends Bundle
{
val cpu_req = new ioDTLB_CPU_req().flip
val cpu_resp = new ioDTLB_CPU_resp()
val ptw = new IOTLBPTW
}
class rocketTLB(entries: Int) extends Component
{
val io = new ioDTLB();
val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_cpu_req_vpn = Reg() { UFix() }
val r_cpu_req_cmd = Reg() { Bits() }
val r_cpu_req_asid = Reg() { UFix() }
val tlb = new TLB(entries)
tlb.io.req.valid := r_cpu_req_val && !io.cpu_req.bits.kill
tlb.io.req.bits.instruction := Bool(false)
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.vpn := r_cpu_req_vpn
tlb.io.req.bits.asid := r_cpu_req_asid
def cmdIsRead(cmd: Bits) = cmd === M_XRD || cmd(3)
def cmdIsWrite(cmd: Bits) = cmd === M_XWR || cmd(3)
def cmdIsPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
def cmdNeedsTLB(cmd: Bits) = cmdIsRead(cmd) || cmdIsWrite(cmd) || cmdIsPrefetch(cmd)
when (io.cpu_req.fire() && cmdNeedsTLB(io.cpu_req.bits.cmd)) {
r_cpu_req_vpn := io.cpu_req.bits.vpn;
r_cpu_req_cmd := io.cpu_req.bits.cmd;
r_cpu_req_asid := io.cpu_req.bits.asid;
r_cpu_req_val := Bool(true);
}
.otherwise {
r_cpu_req_val := Bool(false);
}
io.cpu_req.ready := tlb.io.req.ready && !io.cpu_resp.miss
io.cpu_resp.ppn := tlb.io.resp.ppn
io.cpu_resp.miss := r_cpu_req_val && tlb.io.resp.miss
io.cpu_resp.xcpt_ld := r_cpu_req_val && tlb.io.resp.xcpt_ld && cmdIsRead(r_cpu_req_cmd)
io.cpu_resp.xcpt_st := r_cpu_req_val && tlb.io.resp.xcpt_st && cmdIsWrite(r_cpu_req_cmd)
io.cpu_resp.xcpt_pf := r_cpu_req_val && tlb.io.resp.xcpt_ld && cmdIsPrefetch(r_cpu_req_cmd)
io.ptw <> tlb.io.ptw
}