refactored vector tlb
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9a02298f6f
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@ -44,18 +44,13 @@ class Core(implicit conf: RocketConfiguration) extends Component
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if (HAVE_VEC) {
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val vu = new vu()
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val vdtlb = new rocketTLB(8)
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val vdtlb = new TLB(8)
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ptw += vdtlb.io.ptw
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vdtlb.io.cpu_req <> vu.io.vec_tlb_req
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vu.io.vec_tlb_resp := vdtlb.io.cpu_resp
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vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
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vdtlb.io <> vu.io.vec_tlb
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val pftlb = new rocketTLB(2)
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pftlb.io.cpu_req <> vu.io.vec_pftlb_req
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val pftlb = new TLB(2)
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pftlb.io <> vu.io.vec_pftlb
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ptw += pftlb.io.ptw
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vu.io.vec_pftlb_resp := pftlb.io.cpu_resp
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vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
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dpath.io.vec_ctrl <> ctrl.io.vec_dpath
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@ -12,7 +12,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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val host = new ioHTIF(conf.ntiles)
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val ctrl = new ioCtrlDpath().flip
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val dmem = new ioHellaCache()(conf.dcache)
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val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
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val ptw = new IODatapathPTW().flip
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val imem = new IOCPUFrontend()(conf.icache)
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val fpu = new ioDpathFPU();
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@ -210,7 +209,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
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io.dmem.req.bits.tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val)
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require(io.dmem.req.bits.tag.getWidth >= 6)
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io.dtlb.vpn := ex_effective_address >> UFix(PGIDX_BITS)
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// processor control regfile read
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pcr.io.r.en := io.ctrl.pcr != PCR_N
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@ -82,7 +82,6 @@ class TLBResp(entries: Int) extends Bundle
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val ppn = UFix(OUTPUT, PPN_BITS)
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val xcpt_ld = Bool(OUTPUT)
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val xcpt_st = Bool(OUTPUT)
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val xcpt_pf = Bool(OUTPUT)
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val xcpt_if = Bool(OUTPUT)
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override def clone = new TLBResp(entries).asInstanceOf[this.type]
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@ -180,61 +179,3 @@ class TLB(entries: Int) extends Component
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state := s_ready
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}
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}
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// ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala
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// should keep them in sync
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class ioDTLB_CPU_req_bundle extends TLBReq
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{
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val kill = Bool()
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val cmd = Bits(width=4) // load/store/amo
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}
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class ioDTLB_CPU_req extends FIFOIO()( { new ioDTLB_CPU_req_bundle() } )
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class ioDTLB_CPU_resp extends TLBResp(1)
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class ioDTLB extends Bundle
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{
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val cpu_req = new ioDTLB_CPU_req().flip
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val cpu_resp = new ioDTLB_CPU_resp()
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val ptw = new IOTLBPTW
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}
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class rocketTLB(entries: Int) extends Component
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{
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val io = new ioDTLB();
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_vpn = Reg() { UFix() }
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val r_cpu_req_cmd = Reg() { Bits() }
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val r_cpu_req_asid = Reg() { UFix() }
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val tlb = new TLB(entries)
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tlb.io.req.valid := r_cpu_req_val && !io.cpu_req.bits.kill
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tlb.io.req.bits.instruction := Bool(false)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.vpn := r_cpu_req_vpn
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tlb.io.req.bits.asid := r_cpu_req_asid
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def cmdIsRead(cmd: Bits) = cmd === M_XRD || cmd(3)
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def cmdIsWrite(cmd: Bits) = cmd === M_XWR || cmd(3)
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def cmdIsPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
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def cmdNeedsTLB(cmd: Bits) = cmdIsRead(cmd) || cmdIsWrite(cmd) || cmdIsPrefetch(cmd)
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when (io.cpu_req.fire() && cmdNeedsTLB(io.cpu_req.bits.cmd)) {
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r_cpu_req_vpn := io.cpu_req.bits.vpn;
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r_cpu_req_cmd := io.cpu_req.bits.cmd;
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r_cpu_req_asid := io.cpu_req.bits.asid;
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r_cpu_req_val := Bool(true);
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}
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.otherwise {
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r_cpu_req_val := Bool(false);
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}
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io.cpu_req.ready := tlb.io.req.ready && !io.cpu_resp.miss
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io.cpu_resp.ppn := tlb.io.resp.ppn
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io.cpu_resp.miss := r_cpu_req_val && tlb.io.resp.miss
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io.cpu_resp.xcpt_ld := r_cpu_req_val && tlb.io.resp.xcpt_ld && cmdIsRead(r_cpu_req_cmd)
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io.cpu_resp.xcpt_st := r_cpu_req_val && tlb.io.resp.xcpt_st && cmdIsWrite(r_cpu_req_cmd)
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io.cpu_resp.xcpt_pf := r_cpu_req_val && tlb.io.resp.xcpt_ld && cmdIsPrefetch(r_cpu_req_cmd)
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io.ptw <> tlb.io.ptw
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}
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