riscv/rocket-chip
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  • 8f7b390353 UInt-> Bits; avoid mixed UInt/SInt code Andrew Waterman 2015-07-30 23:46:32 -0700
  • 6c391e3b37 Use UInt(0), not UInt(width=0), for constant 0 Andrew Waterman 2015-07-30 23:45:48 -0700
  • 0c9a7817b6 Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7) Henry Cook 2015-07-30 16:30:00 -0700
  • db7258f887 Add junctions to the possible managed dependency list. Jim Lawson 2015-07-30 15:11:23 -0700
  • 4c0f996808 Fix typo (juntion -> junctions). Jim Lawson 2015-07-30 14:50:28 -0700
  • 51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). Henry Cook 2015-07-29 17:56:19 -0700
  • ee531dc97e Add missing changes to emulator/Makefile Henry Cook 2015-07-29 17:57:02 -0700
  • d2a594fb57 new junctions repo has mem size constants Henry Cook 2015-07-29 17:22:22 -0700
  • c70b495f6d moved buses to junctions repo Henry Cook 2015-07-29 18:04:30 -0700
  • c27945c094 source and build files. source code pulled from uncore and zscale repos Henry Cook 2015-07-29 18:02:58 -0700
  • 9d67ef4ee2 simplify .sbt files Henry Cook 2015-07-28 14:35:26 -0700
  • ce161b83e3 Chisel3 compatibility: avoid subword assignment Andrew Waterman 2015-07-29 15:03:13 -0700
  • c8c312e860 minor btb cleanup Andrew Waterman 2015-07-29 15:03:01 -0700
  • 8b1ab23347 update README.md Henry Cook 2015-07-28 16:12:17 -0700
  • 4daa20b5fe simplify .sbt files Henry Cook 2015-07-28 15:15:34 -0700
  • a2fdcdcaef Use Seq, not Iterable, when traversal order matters Andrew Waterman 2015-07-29 00:24:58 -0700
  • 431dd2219b Another Bits -> BitPat Andrew Waterman 2015-07-28 20:13:56 -0700
  • a69c749249 Fix compilation with scala 2.11.6 Andrew Waterman 2015-07-28 16:24:45 -0700
  • 6a44cd43fd Update README.md Henry Cook 2015-07-28 16:20:18 -0700
  • 8eb20cde44 Update LICENSE Henry Cook 2015-07-28 16:07:30 -0700
  • 2225a6d5b4 Initial commit Henry Cook 2015-07-28 15:52:07 -0700
  • 049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares Andrew Waterman 2015-07-28 02:48:49 -0700
  • f8ec6d6393 Chisel3 compatibility: use BitPat for don't-cares Andrew Waterman 2015-07-28 02:46:23 -0700
  • d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used Henry Cook 2015-07-28 00:23:31 -0700
  • efd6458a3d add zscale programs Yunsup Lee 2015-07-27 19:06:06 -0700
  • e571ebaf7f bump zscale Yunsup Lee 2015-07-27 17:23:38 -0700
  • f2dcc40e67 Chisel3 compatibility changes Andrew Waterman 2015-07-27 12:42:20 -0700
  • 866396545d For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten Henry Cook 2015-07-23 17:00:22 -0700
  • 0e06c941df Chisel3 compatibility fixes Andrew Waterman 2015-07-23 14:58:46 -0700
  • caf89baeb7 update zscale Yunsup Lee 2015-07-23 13:59:45 -0700
  • ae73e3a997 Only instantiate div/sqrt unit if requested Andrew Waterman 2015-07-22 22:17:26 -0700
  • e9433ee01e Minor cleanup Andrew Waterman 2015-07-22 17:32:44 -0700
  • b4e4ceed3d Factor out some more hazard detection code Andrew Waterman 2015-07-22 15:52:13 -0700
  • bd785e7d19 Factor out common hazard detection code Andrew Waterman 2015-07-22 15:46:20 -0700
  • bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS Henry Cook 2015-07-22 11:49:10 -0700
  • cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) Andrew Waterman 2015-07-21 17:10:56 -0700
  • 25e1412a33 Merge pull request #11 from ucb-bar/regression-fixes Andrew Waterman 2015-07-20 12:58:54 -0700
  • d6b29ca9cc Run regression with bash's "-ex" mode Palmer Dabbelt 2015-07-20 12:21:19 -0700
  • 9bbecffbb8 Have regression run "make" before "make run-asm-tests" Palmer Dabbelt 2015-07-20 12:20:32 -0700
  • a99b1e3a01 append config name to generated Makefrag filename Yunsup Lee 2015-07-17 12:34:49 -0700
  • 777facf91e update tools Yunsup Lee 2015-07-17 12:33:19 -0700
  • e7802825c3 add Zscale testing Yunsup Lee 2015-07-17 12:02:02 -0700
  • ac6e73e317 Add Wire() wrap Andrew Waterman 2015-07-15 20:24:18 -0700
  • 3c0475e08b Add Wire() wrap Andrew Waterman 2015-07-15 20:24:03 -0700
  • 2d6b3b2331 Don't use clone Andrew Waterman 2015-07-15 18:06:27 -0700
  • 276f53b652 Delete BigMem; it's not used anymore Andrew Waterman 2015-07-15 17:41:47 -0700
  • 5b7f3c3006 Don't use clone Andrew Waterman 2015-07-15 17:30:50 -0700
  • 1e977d12f2 Update README.md Henry Cook 2015-07-15 16:25:04 -0700
  • f5b3649b73 Merge commit 'd819fb28c3370747475d7c5f4b641723cab1fd0c' into rocc-fpu-port Henry Cook 2015-07-15 15:29:56 -0700
  • 15cec0eab7 Vec(Reg) -> Reg(Vec) Andrew Waterman 2015-07-15 12:44:54 -0700
  • be2ff6dec7 Vec(Reg) -> Reg(Vec) Andrew Waterman 2015-07-15 12:33:46 -0700
  • 4c7c3f5bb2 add test generate for ZscaleTop Yunsup Lee 2015-07-14 16:26:28 -0700
  • d6df479870 move 'include /Makefrag' out of top-level Makefrag Yunsup Lee 2015-07-14 16:13:32 -0700
  • 76046c52fe Cleanup testing rv64uf Henry Cook 2015-07-13 18:56:18 -0700
  • 186e32a546 Merge pull request #9 from ucb-bar/param-based-makefrags Henry Cook 2015-07-13 15:51:28 -0700
  • 302cd3e638 Added BuildZscale param for use in Top and makefrag generation Henry Cook 2015-07-13 15:46:42 -0700
  • 407d8e473e first cut at parameter-based testing Henry Cook 2015-07-13 14:54:26 -0700
  • a78e28523c Chisel3: Don't mix Mux types Andrew Waterman 2015-07-11 14:06:08 -0700
  • e76a9d3493 Chisel3: Don't mix Mux types Andrew Waterman 2015-07-11 14:05:39 -0700
  • 5dc3da008e Use Chisel3 SeqMem construct Andrew Waterman 2015-07-11 13:36:14 -0700
  • 3233867390 Use Chisel3 SeqMem construct Andrew Waterman 2015-07-11 13:32:45 -0700
  • 4e4015089d rename Configs source Henry Cook 2015-07-09 15:04:11 -0700
  • 3573fcdf2d bump uncore Henry Cook 2015-07-09 14:42:38 -0700
  • fb91e3e1ab minor metadata API update (0.3.3) Henry Cook 2015-07-09 14:35:39 -0700
  • 80ad1eac70 Update README.md Henry Cook 2015-07-08 19:05:18 -0700
  • 09e29e8fe0 add zscale Yunsup Lee 2015-07-07 20:38:47 -0700
  • e6a13cdeba New machine-mode timer facility Yunsup Lee 2015-07-07 17:26:07 -0700
  • 4fbb0f80ff Added some multicore/multibanks named ChiselConfigs Henry Cook 2015-07-06 18:21:06 -0700
  • 854fd64fba Added optional Makefile includes for private chip repos Henry Cook 2015-07-06 17:15:27 -0700
  • 5ed2899e56 Merge pull request #10 from wsong83/fix Henry Cook 2015-07-06 15:18:49 -0700
  • 5362e2bbbd New machine-mode timer facility Andrew Waterman 2015-07-05 16:38:49 -0700
  • 55059632c4 Temporarily use HTIF to push RTC value to cores Andrew Waterman 2015-07-05 16:19:39 -0700
  • d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. Henry Cook 2015-06-25 23:17:35 -0700
  • d7cb60e8fa L2 WritebackUnit bug fix Henry Cook 2015-07-02 13:52:40 -0700
  • 12d8d8c5e3 Merge pull request #8 from seldridge/master Scott Beamer 2015-06-28 08:54:24 -0500
  • b4cd8c5981 Fix vlsi_mem_gen for Python 2 or 3 Schuyler Eldridge 2015-06-25 12:48:31 -0700
  • a42832fc70 Fix fpga_mem_gen for Python 2 and 3 Environments Schuyler Eldridge 2015-06-25 10:40:59 -0700
  • b4e38192a1 Fix (?) L2$ miss bug Andrew Waterman 2015-06-24 18:01:56 -0700
  • 5e009ecc75 Fix an apparently benign PC sign-extension bug Andrew Waterman 2015-06-11 16:08:18 -0700
  • ea76800d1a Fix data array reset bug Andrew Waterman 2015-06-11 15:28:23 -0700
  • 4b6cd7f3eb Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7 Colin Schmidt 2015-06-03 15:51:53 -0700
  • 4db60d9e9d code clean in dcache, no need to check the condition twice. Wei Song 2015-06-02 22:06:12 +0100
  • b6e68773fd nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array. Wei Song 2015-05-30 16:25:27 +0100
  • f3a838cedf nasti converters, hub bugfix Henry Cook 2015-05-19 18:40:34 -0700
  • a59ba39310 bump submodule for fpga-zynq Scott Beamer 2015-05-21 11:26:57 -0700
  • 38edbc78e5 Merge pull request #5 from amsharifian/master Scott Beamer 2015-05-21 11:24:25 -0700
  • 6a9390c50e Avoid spurious D$ assertion failures Andrew Waterman 2015-05-19 02:56:20 -0700
  • f460cb6c54 Update to privileged architecture 1.7 Andrew Waterman 2015-05-18 18:23:58 -0700
  • 254498042a Fix Split for 0-width wires Andrew Waterman 2015-05-18 18:23:17 -0700
  • d31b26c342 Clean up handling of icache's io.cpu.npc signal Andrew Waterman 2015-05-18 18:22:48 -0700
  • c202449e34 first version NASTI IOs Henry Cook 2015-05-14 15:29:49 -0700
  • 90c9ee7b04 fix unalloc putblocks Henry Cook 2015-05-14 12:37:35 -0700
  • a7fa77c7fc track operand size for Gets Henry Cook 2015-05-13 23:28:18 -0700
  • 172c372d3e L2 alloc cleanup Henry Cook 2015-05-12 17:14:06 -0700
  • 5fdae2cb61 Merge branch 'master' of github.com:ucb-bar/uncore Henry Cook 2015-05-07 16:18:23 -0700
  • fc883b5049 rm index.html Henry Cook 2015-05-07 16:17:40 -0700
  • 8362eba00f Merge branch 'gh-pages' Henry Cook 2015-05-07 16:16:13 -0700
  • aec24cf1a7 readme Henry Cook 2015-05-07 16:16:07 -0700
  • 62b6f24798 Delete TileLink0.3.1Specification.pdf Henry Cook 2015-05-07 15:43:06 -0700
  • 90ced93eeb Merge branch 'master' into gh-pages Henry Cook 2015-05-07 12:35:14 -0700