add Zscale testing

fsim/Makefile

@@ -17,6 +17,7 @@ output_dir = $(sim_dir)/output
 
 BACKEND ?= fpga
 CONFIG ?= DefaultFPGAConfig
+TB ?= rocketTestHarness
 
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag

fsim/Makefrag

@@ -9,7 +9,7 @@ sim_vsrcs = \
 	$(generated_dir)/$(MODEL).$(CONFIG).v \
 	$(generated_dir)/consts.$(CONFIG).vh \
 	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
-	$(base_dir)/vsrc/rocketTestHarness.v \
+	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/backup_mem.v \
 
 # C sources
@@ -45,7 +45,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(sim_dir)/libdramsim.a \
 	+define+FPGA \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND=rocketTestHarness.verbose \
+	+define+PRINTF_COND=$(TB).verbose \
 	+libext+.v \
 
 #--------------------------------------------------------------------

src/main/scala/Configs.scala

@@ -218,6 +218,8 @@ class WithZscale extends ChiselConfig(
       (r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
     }
     case UseZscale => true
+    case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
+    case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
   }
 )
 

src/main/scala/ZscaleChip.scala

@@ -9,6 +9,8 @@ import zscale._
 
 case object UseZscale extends Field[Boolean]
 case object BuildZscale extends Field[(Bool) => Zscale]
+case object BootROMCapacity extends Field[Int]
+case object DRAMCapacity extends Field[Int]
 
 class ZscaleSystem extends Module {
   val io = new Bundle {
@@ -63,8 +65,8 @@ class ZscaleTop extends Module {
   }
 
   val sys = Module(new ZscaleSystem)
-  val bootmem = Module(new HASTISRAM(4096))
-  val dram = Module(new HASTISRAM(4194304))
+  val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4))
+  val dram = Module(new HASTISRAM(params(DRAMCapacity)/4))
 
   sys.io.host <> io.host
   bootmem.io <> sys.io.bootmem

vsim/Makefile

@@ -17,6 +17,7 @@ output_dir = $(sim_dir)/output
 
 BACKEND ?= rocketchip.RocketChipBackend
 CONFIG ?= DefaultVLSIConfig
+TB ?= rocketTestHarness
 
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag

vsim/Makefrag

@@ -8,7 +8,7 @@ sim_vsrcs = \
 	$(generated_dir)/$(MODEL).$(CONFIG).v \
 	$(generated_dir)/consts.$(CONFIG).vh \
 	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
-	$(base_dir)/vsrc/rocketTestHarness.v \
+	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/backup_mem.v \
 
 # C sources
@@ -43,7 +43,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND=rocketTestHarness.verbose \
+	+define+PRINTF_COND=$(TB).verbose \
 	+libext+.v \
 
 #--------------------------------------------------------------------

vsrc/ZscaleTestHarness.v

@@ -0,0 +1,101 @@
+// See LICENSE for license details.
+//
+module ZscaleTestHarness;
+
+  reg clk   = 0;
+  reg reset = 1;
+
+  always #`CLOCK_PERIOD clk = ~clk;
+
+  wire        csr_resp_valid;
+  wire [31:0] dummy;
+  wire [31:0] csr_resp_bits;
+
+  ZscaleTop dut
+  (
+    .clk(clk),
+    .reset(reset),
+    .io_host_reset(reset),
+
+    .io_host_id(1'd0),
+    .io_host_pcr_req_ready(),
+    .io_host_pcr_req_valid(1'b1),
+    .io_host_pcr_req_bits_rw(1'b0),
+    .io_host_pcr_req_bits_addr(12'h780), // tohost register
+    .io_host_pcr_req_bits_data({dummy, 32'd0}),
+    .io_host_pcr_rep_ready(1'b1),
+    .io_host_pcr_rep_valid(csr_resp_valid),
+    .io_host_pcr_rep_bits({dummy, csr_resp_bits}),
+    
+    .io_host_ipi_req_ready(1'b1),
+    .io_host_ipi_req_valid(),
+    .io_host_ipi_req_bits(),
+    .io_host_ipi_rep_ready(),
+    .io_host_ipi_rep_valid(1'b0),
+    .io_host_ipi_rep_bits()
+  );
+
+  reg [1023:0] loadmem = 0;
+  reg [1023:0] vcdplusfile = 0;
+  reg [  63:0] max_cycles = 0;
+  reg [  63:0] trace_count = 0;
+  reg          verbose = 0;
+  integer      stderr = 32'h80000002;
+  integer      i;
+  reg [127:0]  image [8191:0];
+
+  initial
+  begin
+    $value$plusargs("max-cycles=%d", max_cycles);
+    verbose = $test$plusargs("verbose");
+    if ($value$plusargs("loadmem=%s", loadmem))
+    begin
+      $readmemh(loadmem, image);
+    end
+    if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
+    begin
+      $vcdplusfile(vcdplusfile);
+      $vcdpluson(0);
+      $vcdplusmemon(0);
+    end
+
+    #0.5;
+    for (i=0; i<`BOOT_CAPACITY/16; i=i+1) begin
+      dut.bootmem.ram.ram[4*i+0] = image[i][31:0];
+      dut.bootmem.ram.ram[4*i+1] = image[i][63:32];
+      dut.bootmem.ram.ram[4*i+2] = image[i][95:64];
+      dut.bootmem.ram.ram[4*i+3] = image[i][127:96];
+    end
+
+    #777.7 reset = 0;
+  end
+
+  reg [255:0] reason = 0;
+  always @(posedge clk)
+  begin
+    trace_count = trace_count + 1;
+
+    if (max_cycles > 0 && trace_count > max_cycles)
+      reason = "timeout";
+
+    if (!reset)
+    begin
+      if (csr_resp_valid && csr_resp_bits > 1)
+        $sformat(reason, "tohost = %d", csr_resp_bits >> 1);
+
+      if (csr_resp_valid && csr_resp_bits == 1)
+      begin
+        $vcdplusclose;
+        $finish;
+      end
+    end
+
+    if (reason)
+    begin
+      $fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
+      $vcdplusclose;
+      $finish;
+    end
+  end
+
+endmodule