add zscale

only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now

.gitmodules

@@ -19,3 +19,6 @@
 [submodule "fpga-zynq"]
 	path = fpga-zynq
 	url = https://github.com/ucb-bar/fpga-zynq.git
+[submodule "zscale"]
+	path = zscale
+	url = https://github.com/ucb-bar/zscale

Makefrag

@@ -30,7 +30,7 @@ timeout_cycles = 100000000
 #--------------------------------------------------------------------
 
 $(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs)
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --W0W --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)"
 	cd $(generated_dir) && \
 	if [ -a $(MODEL).$(CONFIG).conf ]; then \
 	  $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
@@ -43,7 +43,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
 	echo "\`endif // CONST_VH" >> $@
 
 $(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
 
 #--------------------------------------------------------------------
 # DRAMSim2

project/build.scala

@@ -31,8 +31,9 @@ object BuildSettings extends Build {
   lazy val hardfloat  = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
   lazy val uncore     = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
   lazy val rocket     = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
+  lazy val zscale     = Project("zscale", file("zscale"), settings = buildSettings) dependsOn(rocket)
 
-  val baselist = Vector("chisel", "uncore", "rocket", "hardfloat")
+  val baselist = Vector("chisel", "uncore", "rocket", "zscale", "hardfloat")
   def getsubdirs = {
     val blacklist = (baselist ++ Vector("target", "project"))
     IO.listFiles(file(".")) map (_.toString.split("/").last) filter (f=> !blacklist.contains(f) && (f(0)!='.')) filter (f=> !IO.listFiles(file(f+"/src/main/scala")).isEmpty)
@@ -54,8 +55,8 @@ object BuildSettings extends Build {
   lazy val addons     = Project("addons", file(".addons-dont-touch"), settings = buildSettings ++ Seq(
     prepareTask := prepareTaskImpl,
     (compile in Compile) <<= (compile in Compile) dependsOn (prepareTask)
-  )) dependsOn(chisel, hardfloat, uncore, rocket)
-  lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings).dependsOn(chisel, uncore, rocket, addons)
+  )) dependsOn(chisel, hardfloat, uncore, rocket, zscale)
+  lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings).dependsOn(chisel, uncore, rocket, zscale, addons)
 
   val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
   val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")

src/main/scala/ZscaleChip.scala

@@ -0,0 +1,69 @@
+// See LICENSE for license details.
+
+package rocketchip
+
+import Chisel._
+import uncore._
+import rocket._
+import zscale._
+
+class ZscaleSystem extends Module {
+  val io = new Bundle {
+    val host = new HTIFIO
+    val jtag = new HASTIMasterIO().flip
+    val bootmem = new HASTISlaveIO().flip
+    val dram = new HASTISlaveIO().flip
+    val spi = new HASTISlaveIO().flip
+    val led = new POCIIO
+    val corereset = new POCIIO
+  }
+
+  val core = Module(new Zscale(io.host.reset), {case TLId => "L1ToL2"})
+
+  val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
+
+  val sbus_afn = (addr: UInt) => addr(31, 29).orR
+  val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
+  val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
+
+  val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
+  val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
+  val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
+
+  val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn)))
+  val sadapter = Module(new HASTISlaveToMaster)
+  val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn)))
+  val padapter = Module(new HASTItoPOCIBridge)
+  val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn)))
+
+  core.io.host <> io.host
+  xbar.io.masters(0) <> io.jtag
+  xbar.io.masters(1) <> core.io.dmem
+  xbar.io.masters(2) <> core.io.imem
+
+  io.bootmem <> xbar.io.slaves(0)
+  sadapter.io.in <> xbar.io.slaves(1)
+
+  sbus.io.master <> sadapter.io.out
+  io.dram <> sbus.io.slaves(0)
+  io.spi <> sbus.io.slaves(1)
+  padapter.io.in <> sbus.io.slaves(2)
+
+  pbus.io.master <> padapter.io.out
+  io.led <> pbus.io.slaves(0)
+  io.corereset <> pbus.io.slaves(1)
+}
+
+class ZscaleTop extends Module {
+  val io = new Bundle {
+    val host = new HTIFIO
+  }
+
+  val sys = Module(new ZscaleSystem)
+  val bootmem = Module(new HASTISRAM(4096))
+  val dram = Module(new HASTISRAM(4194304))
+
+  sys.io.host <> io.host
+  bootmem.io <> sys.io.bootmem
+  dram.io <> sys.io.dram
+}

zscale

@@ -0,0 +1 @@
+Subproject commit 81f351bc9c59f2de26e2062f65079e9e72b37e59