Update README.md
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@ -7,6 +7,5 @@ the your chip repository and add it as Project in your chip's build.scala.
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These components are only dependent on Chisel, i.e.
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lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
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Documentation for the uncore library is available <a href="http://ucb-bar.github.io/uncore/latest/api/">here</a>
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and an overview of the TileLink Protocol is available <a href="https://docs.google.com/document/d/1Iczcjigc-LUi8QmDPwnAu1kH4Rrt6Kqi1_EUaCrfrk8/pub">here</a>
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ScalaDoc for the uncore library is available <a href="http://ucb-bar.github.io/uncore/latest/api/">here</a>
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and an overview of the TileLink Protocol is available <a href="https://docs.google.com/document/d/1Iczcjigc-LUi8QmDPwnAu1kH4Rrt6Kqi1_EUaCrfrk8/pub">here</a>, with associated CoherencePolicy documentation <a href="https://docs.google.com/document/d/1vBPgrlvuLmvCB33dVb1wr3xc9f8uOrNzZ9AFMGHeSkg/pub">here</a>.
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