New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
This commit is contained in:
1
Makefrag
1
Makefrag
@ -162,7 +162,6 @@ asm_p_tests = \
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rv64si-p-ma_addr \
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rv64si-p-scall \
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rv64si-p-sbreak \
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rv64si-p-timer \
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rv64ui-pm-lrsc \
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rv64mi-p-csr \
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rv64mi-p-mcsr \
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Submodule riscv-tools updated: 8a16e34810...7e8f164418
2
rocket
2
rocket
Submodule rocket updated: 4ad41b4b63...d819fb28c3
@ -98,6 +98,7 @@ class DefaultConfig extends ChiselConfig (
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLNManagers) + site(TLNClients)
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case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
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case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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2
uncore
2
uncore
Submodule uncore updated: bf608ce914...1894adb89d
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