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Merge pull request #8 from seldridge/master 

Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
This commit is contained in:
Scott Beamer 2015-06-28 08:54:24 -05:00
parent a59ba39310 b4cd8c5981
commit 12d8d8c5e3
2 changed files with 5 additions and 5 deletions
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4
fsim/fpga_mem_gen
View File

@ -53,7 +53,7 @@ def parse_line(line):
mask_gran = 1
tokens = line.split()
i = 0
for i in xrange(0,len(tokens),2):
for i in range(0,len(tokens),2):
s = tokens[i]
if s == 'name':
name = tokens[i+1]
@ -188,7 +188,7 @@ def main():
if len(sys.argv) < 2:
sys.exit('Please give a .conf file as input')
for line in open(sys.argv[1]):
print gen_mem(*parse_line(line))
print(gen_mem(*parse_line(line)))
if __name__ == '__main__':

6
vsim/vlsi_mem_gen
View File

@ -15,7 +15,7 @@ def parse_line(line):
mask_gran = 1
tokens = line.split()
i = 0
for i in xrange(0,len(tokens),2):
for i in range(0,len(tokens),2):
s = tokens[i]
if s == 'name':
name = tokens[i+1]
@ -130,7 +130,7 @@ def gen_mem(name, width, depth, ports):
%s\n\
end\n\
%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
s = "module %s(\n\
%s\n\
);\n\
@ -144,7 +144,7 @@ def main():
if len(sys.argv) < 2:
sys.exit('Please give a .conf file as input')
for line in open(sys.argv[1]):
print gen_mem(*parse_line(line))
print(gen_mem(*parse_line(line)))
if __name__ == '__main__':
main()