source and build files. source code pulled from uncore and zscale repos

junctions/build.sbt

@@ -0,0 +1,19 @@
+organization := "edu.berkeley.cs"
+
+version := "1.0"
+
+name := "junctions"
+
+scalaVersion := "2.10.2"
+
+// Provide a managed dependency on chisel if -DchiselVersion="" is supplied on the command line.
+libraryDependencies ++= (Seq("chisel").map {
+  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten
+
+site.settings
+
+site.includeScaladoc()
+
+ghpages.settings
+
+git.remoteRepo := "git@github.com:ucb-bar/junctions.git"

junctions/project/plugins.sbt

@@ -0,0 +1,5 @@
+resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
+
+addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.3")
+
+addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.1")

junctions/src/main/scala/hasti.scala

@@ -0,0 +1,250 @@
+package junctions
+
+import Chisel._
+
+abstract trait HASTIConstants
+{
+  val SZ_HTRANS     = 2
+  val HTRANS_IDLE   = UInt(0, SZ_HTRANS)
+  val HTRANS_BUSY   = UInt(1, SZ_HTRANS)
+  val HTRANS_NONSEQ = UInt(2, SZ_HTRANS)
+  val HTRANS_SEQ    = UInt(3, SZ_HTRANS)
+
+  val SZ_HBURST     = 3
+  val HBURST_SINGLE = UInt(0, SZ_HBURST)
+  val HBURST_INCR   = UInt(1, SZ_HBURST)
+  val HBURST_WRAP4  = UInt(2, SZ_HBURST)
+  val HBURST_INCR4  = UInt(3, SZ_HBURST)
+  val HBURST_WRAP8  = UInt(4, SZ_HBURST)
+  val HBURST_INCR8  = UInt(5, SZ_HBURST)
+  val HBURST_WRAP16 = UInt(6, SZ_HBURST)
+  val HBURST_INCR16 = UInt(7, SZ_HBURST)
+
+  val SZ_HRESP      = 1
+  val HRESP_OKAY    = UInt(0, SZ_HRESP)
+  val HRESP_ERROR   = UInt(1, SZ_HRESP)
+
+  val SZ_HSIZE = 3
+  val SZ_HPROT = 4
+
+  // TODO: Parameterize
+  val SZ_HADDR = 32
+  val SZ_HDATA = 32
+
+  def dgate(valid: Bool, b: Bits) = Fill(b.getWidth, valid) & b
+}
+
+class HASTIMasterIO extends Bundle
+{
+  val haddr     = UInt(OUTPUT, SZ_HADDR)
+  val hwrite    = Bool(OUTPUT)
+  val hsize     = UInt(OUTPUT, SZ_HSIZE)
+  val hburst    = UInt(OUTPUT, SZ_HBURST)
+  val hprot     = UInt(OUTPUT, SZ_HPROT)
+  val htrans    = UInt(OUTPUT, SZ_HTRANS)
+  val hmastlock = Bool(OUTPUT)
+
+  val hwdata = Bits(OUTPUT, SZ_HDATA)
+  val hrdata = Bits(INPUT, SZ_HDATA)
+
+  val hready = Bool(INPUT)
+  val hresp  = UInt(INPUT, SZ_HRESP)
+}
+
+class HASTISlaveIO extends Bundle
+{
+  val haddr     = UInt(INPUT, SZ_HADDR)
+  val hwrite    = Bool(INPUT)
+  val hsize     = UInt(INPUT, SZ_HSIZE)
+  val hburst    = UInt(INPUT, SZ_HBURST)
+  val hprot     = UInt(INPUT, SZ_HPROT)
+  val htrans    = UInt(INPUT, SZ_HTRANS)
+  val hmastlock = Bool(INPUT)
+
+  val hwdata = Bits(INPUT, SZ_HDATA)
+  val hrdata = Bits(OUTPUT, SZ_HDATA)
+
+  val hsel      = Bool(INPUT)
+  val hreadyin  = Bool(INPUT)
+  val hreadyout = Bool(OUTPUT)
+  val hresp     = UInt(OUTPUT, SZ_HRESP)
+}
+
+class HASTIBus(amap: Seq[UInt=>Bool]) extends Module
+{
+  val io = new Bundle {
+    val master = new HASTIMasterIO().flip
+    val slaves = Vec.fill(amap.size){new HASTISlaveIO}.flip
+  }
+
+  // skid buffer
+  val skb_valid = Reg(init = Bool(false))
+  val skb_haddr = Reg(UInt(width = SZ_HADDR))
+  val skb_hwrite = Reg(Bool())
+  val skb_hsize = Reg(UInt(width = SZ_HSIZE))
+  val skb_hburst = Reg(UInt(width = SZ_HBURST))
+  val skb_hprot = Reg(UInt(width = SZ_HPROT))
+  val skb_htrans = Reg(UInt(width = SZ_HTRANS))
+  val skb_hmastlock = Reg(Bool())
+  val skb_hwdata = Reg(UInt(width = SZ_HDATA))
+
+  val master_haddr = Mux(skb_valid, skb_haddr, io.master.haddr)
+  val master_hwrite = Mux(skb_valid, skb_hwrite, io.master.hwrite)
+  val master_hsize = Mux(skb_valid, skb_hsize, io.master.hsize)
+  val master_hburst = Mux(skb_valid, skb_hburst, io.master.hburst)
+  val master_hprot = Mux(skb_valid, skb_hprot, io.master.hprot)
+  val master_htrans = Mux(skb_valid, skb_htrans, io.master.htrans)
+  val master_hmastlock = Mux(skb_valid, skb_hmastlock, io.master.hmastlock)
+  val master_hwdata = Mux(skb_valid, skb_hwdata, io.master.hwdata)
+
+  val hsels = PriorityEncoderOH(
+    (io.slaves zip amap) map { case (s, afn) => {
+      s.haddr := master_haddr
+      s.hwrite := master_hwrite
+      s.hsize := master_hsize
+      s.hburst := master_hburst
+      s.hprot := master_hprot
+      s.htrans := master_htrans
+      s.hmastlock := master_hmastlock
+      s.hwdata := master_hwdata
+      afn(master_haddr) && master_htrans.orR
+    }})
+
+  (io.slaves zip hsels) foreach { case (s, hsel) => {
+    s.hsel := hsel
+    s.hreadyin := skb_valid || io.master.hready
+  } }
+
+  val s1_hsels = Vec.fill(amap.size){Reg(init = Bool(false))}
+  val hreadyouts = io.slaves.map(_.hreadyout)
+  val master_hready = s1_hsels.reduce(_||_) === Bool(false) || Mux1H(s1_hsels, hreadyouts)
+
+  when (master_hready) {
+    val skid = s1_hsels.reduce(_||_) && (hsels zip hreadyouts).map{ case (s, r) => s && !r }.reduce(_||_)
+    skb_valid := skid
+    when (skid) {
+      skb_haddr := io.master.haddr
+      skb_hwrite := io.master.hwrite
+      skb_hsize := io.master.hsize
+      skb_hburst := io.master.hburst
+      skb_hprot := io.master.hprot
+      skb_htrans := io.master.htrans
+      skb_hmastlock := io.master.hmastlock
+    }
+
+    (s1_hsels zip hsels) foreach { case (s1, s) =>
+      s1 := s
+    }
+  }
+
+  io.master.hready := !skb_valid && master_hready
+  io.master.hrdata := Mux1H(s1_hsels, io.slaves.map(_.hrdata))
+  io.master.hresp := Mux1H(s1_hsels, io.slaves.map(_.hresp))
+}
+
+class HASTISlaveMux(n: Int) extends Module
+{
+  val io = new Bundle {
+    val ins = Vec.fill(n){new HASTISlaveIO}
+    val out = new HASTISlaveIO().flip
+  }
+
+  // skid buffers
+  val skb_valid = Vec.fill(n){Reg(init = Bool(false))}
+  val skb_haddr = Vec.fill(n){Reg(UInt(width = SZ_HADDR))}
+  val skb_hwrite = Vec.fill(n){Reg(Bool())}
+  val skb_hsize = Vec.fill(n){Reg(UInt(width = SZ_HSIZE))}
+  val skb_hburst = Vec.fill(n){Reg(UInt(width = SZ_HBURST))}
+  val skb_hprot = Vec.fill(n){Reg(UInt(width = SZ_HPROT))}
+  val skb_htrans = Vec.fill(n){Reg(UInt(width = SZ_HTRANS))}
+  val skb_hmastlock = Vec.fill(n){Reg(Bool())}
+
+  val requests = (io.ins zip skb_valid) map { case (in, v) => in.hsel && in.hreadyin || v }
+  val grants = PriorityEncoderOH(requests)
+
+  val s1_grants = Vec.fill(n){Reg(init = Bool(true))}
+
+  (s1_grants zip grants) foreach { case (g1, g) =>
+    when (io.out.hreadyout) { g1 := g }
+  }
+
+  def sel[T <: Data](in: Vec[T], s1: Vec[T]) =
+    Vec((skb_valid zip s1 zip in) map { case ((v, s), in) => Mux(v, s, in) })
+
+  io.out.haddr := Mux1H(grants, sel(Vec(io.ins.map(_.haddr)), skb_haddr))
+  io.out.hwrite := Mux1H(grants, sel(Vec(io.ins.map(_.hwrite)), skb_hwrite))
+  io.out.hsize := Mux1H(grants, sel(Vec(io.ins.map(_.hsize)), skb_hsize))
+  io.out.hburst := Mux1H(grants, sel(Vec(io.ins.map(_.hburst)), skb_hburst))
+  io.out.hprot := Mux1H(grants, sel(Vec(io.ins.map(_.hprot)), skb_hprot))
+  io.out.htrans := Mux1H(grants, sel(Vec(io.ins.map(_.htrans)), skb_htrans))
+  io.out.hmastlock := Mux1H(grants, sel(Vec(io.ins.map(_.hmastlock)), skb_hmastlock))
+  io.out.hsel := grants.reduce(_||_)
+
+  (io.ins zipWithIndex) map { case (in, i) => {
+    when (io.out.hreadyout) {
+      when (grants(i)) {
+        skb_valid(i) := Bool(false)
+      }
+      when (!grants(i) && !skb_valid(i)) {
+        val valid = in.hsel && in.hreadyin
+        skb_valid(i) := valid
+        when (valid) { // clock-gate
+          skb_haddr(i) := in.haddr
+          skb_hwrite(i) := in.hwrite
+          skb_hsize(i) := in.hsize
+          skb_hburst(i) := in.hburst
+          skb_hprot(i) := in.hprot
+          skb_htrans(i) := in.htrans
+          skb_hmastlock(i) := in.hmastlock
+        }
+      }
+    }
+  } }
+
+  io.out.hwdata := Mux1H(s1_grants, io.ins.map(_.hwdata))
+  io.out.hreadyin := io.out.hreadyout
+
+  (io.ins zipWithIndex) foreach { case (in, i) => {
+    val g1 = s1_grants(i)
+    in.hrdata := dgate(g1, io.out.hrdata)
+    in.hreadyout := io.out.hreadyout && (!skb_valid(i) || g1)
+    in.hresp := dgate(g1, io.out.hresp)
+  } }
+}
+
+class HASTIXbar(nMasters: Int, addressMap: Seq[UInt=>Bool]) extends Module
+{
+  val io = new Bundle {
+    val masters = Vec.fill(nMasters){new HASTIMasterIO}.flip
+    val slaves = Vec.fill(addressMap.size){new HASTISlaveIO}.flip
+  }
+
+  val buses = List.fill(nMasters){Module(new HASTIBus(addressMap))}
+  val muxes = List.fill(addressMap.size){Module(new HASTISlaveMux(nMasters))}
+
+  (buses.map(b => b.io.master) zip io.masters) foreach { case (b, m) => b <> m }
+  (muxes.map(m => m.io.out)    zip io.slaves ) foreach { case (x, s) => x <> s }
+  for (m <- 0 until nMasters; s <- 0 until addressMap.size) yield {
+    buses(m).io.slaves(s) <> muxes(s).io.ins(m)
+  }
+}
+
+class HASTISlaveToMaster extends Module
+{
+  val io = new Bundle {
+    val in = new HASTISlaveIO
+    val out = new HASTIMasterIO
+  }
+
+  io.out.haddr := io.in.haddr
+  io.out.hwrite := io.in.hwrite
+  io.out.hsize := io.in.hsize
+  io.out.hburst := io.in.hburst
+  io.out.hprot := io.in.hprot
+  io.out.htrans := Mux(io.in.hsel && io.in.hreadyin, io.in.htrans, HTRANS_IDLE)
+  io.out.hmastlock := io.in.hmastlock
+  io.out.hwdata := io.in.hwdata
+  io.in.hrdata := io.out.hrdata
+  io.in.hreadyout := io.out.hready
+  io.in.hresp := io.out.hresp
+}

junctions/src/main/scala/memserdes.scala

@@ -0,0 +1,374 @@
+// See LICENSE for license details.
+
+package junctions
+import Chisel._
+import scala.math._
+
+case object PAddrBits extends Field[Int]
+case object VAddrBits extends Field[Int]
+case object PgIdxBits extends Field[Int]
+case object PgLevels extends Field[Int]
+case object PgLevelBits extends Field[Int]
+case object ASIdBits extends Field[Int]
+case object PPNBits extends Field[Int]
+case object VPNBits extends Field[Int]
+
+case object MIFAddrBits extends Field[Int]
+case object MIFDataBits extends Field[Int]
+case object MIFTagBits extends Field[Int]
+case object MIFDataBeats extends Field[Int]
+
+trait MIFParameters extends UsesParameters {
+  val mifTagBits = params(MIFTagBits)
+  val mifAddrBits = params(MIFAddrBits)
+  val mifDataBits = params(MIFDataBits)
+  val mifDataBeats = params(MIFDataBeats)
+}
+ 
+abstract class MIFBundle extends Bundle with MIFParameters
+abstract class MIFModule extends Module with MIFParameters
+
+trait HasMemData extends MIFBundle {
+  val data = Bits(width = mifDataBits)
+}
+
+trait HasMemAddr extends MIFBundle {
+  val addr = UInt(width = mifAddrBits)
+}
+
+trait HasMemTag extends MIFBundle {
+  val tag = UInt(width = mifTagBits)
+}
+
+class MemReqCmd extends HasMemAddr with HasMemTag {
+  val rw = Bool()
+}
+
+class MemTag extends HasMemTag
+class MemData extends HasMemData
+class MemResp extends HasMemData with HasMemTag
+
+class MemIO extends Bundle {
+  val req_cmd  = Decoupled(new MemReqCmd)
+  val req_data = Decoupled(new MemData)
+  val resp     = Decoupled(new MemResp).flip
+}
+
+class MemPipeIO extends Bundle {
+  val req_cmd  = Decoupled(new MemReqCmd)
+  val req_data = Decoupled(new MemData)
+  val resp     = Valid(new MemResp).flip
+}
+
+class MemSerializedIO(w: Int) extends Bundle {
+  val req = Decoupled(Bits(width = w))
+  val resp = Valid(Bits(width = w)).flip
+}
+
+class MemSerdes(w: Int) extends MIFModule
+{
+  val io = new Bundle {
+    val wide = new MemIO().flip
+    val narrow = new MemSerializedIO(w)
+  }
+  val abits = io.wide.req_cmd.bits.toBits.getWidth
+  val dbits = io.wide.req_data.bits.toBits.getWidth
+  val rbits = io.wide.resp.bits.getWidth
+
+  val out_buf = Reg(Bits())
+  val in_buf = Reg(Bits())
+
+  val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(UInt(), 5)
+  val state = Reg(init=s_idle)
+  val send_cnt = Reg(init=UInt(0, log2Up((max(abits, dbits)+w-1)/w)))
+  val data_send_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
+  val adone = io.narrow.req.ready && send_cnt === UInt((abits-1)/w)
+  val ddone = io.narrow.req.ready && send_cnt === UInt((dbits-1)/w)
+
+  when (io.narrow.req.valid && io.narrow.req.ready) {
+    send_cnt := send_cnt + UInt(1)
+    out_buf := out_buf >> UInt(w)
+  }
+  when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
+    out_buf := io.wide.req_cmd.bits.toBits
+  }
+  when (io.wide.req_data.valid && io.wide.req_data.ready) {
+    out_buf := io.wide.req_data.bits.toBits
+  }
+
+  io.wide.req_cmd.ready := state === s_idle
+  io.wide.req_data.ready := state === s_write_idle
+  io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
+  io.narrow.req.bits := out_buf
+
+  when (state === s_idle && io.wide.req_cmd.valid) {
+    state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
+  }
+  when (state === s_read_addr && adone) {
+    state := s_idle
+    send_cnt := UInt(0)
+  }
+  when (state === s_write_addr && adone) {
+    state := s_write_idle
+    send_cnt := UInt(0)
+  }
+  when (state === s_write_idle && io.wide.req_data.valid) {
+    state := s_write_data
+  }
+  when (state === s_write_data && ddone) {
+    data_send_cnt := data_send_cnt + UInt(1)
+    state := Mux(data_send_cnt === UInt(mifDataBeats-1), s_idle, s_write_idle)
+    send_cnt := UInt(0)
+  }
+
+  val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
+  val data_recv_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
+  val resp_val = Reg(init=Bool(false))
+
+  resp_val := Bool(false)
+  when (io.narrow.resp.valid) {
+    recv_cnt := recv_cnt + UInt(1)
+    when (recv_cnt === UInt((rbits-1)/w)) {
+      recv_cnt := UInt(0)
+      data_recv_cnt := data_recv_cnt + UInt(1)
+      resp_val := Bool(true)
+    }
+    in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+w-1)/w*w-1,w))
+  }
+
+  io.wide.resp.valid := resp_val
+  io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
+}
+
+class MemDesserIO(w: Int) extends Bundle {
+  val narrow = new MemSerializedIO(w).flip
+  val wide = new MemIO
+}
+
+class MemDesser(w: Int) extends Module // test rig side
+{
+  val io = new MemDesserIO(w)
+  val abits = io.wide.req_cmd.bits.toBits.getWidth
+  val dbits = io.wide.req_data.bits.toBits.getWidth
+  val rbits = io.wide.resp.bits.getWidth
+  val mifDataBeats = params(MIFDataBeats)
+
+  require(dbits >= abits && rbits >= dbits)
+  val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
+  val data_recv_cnt = Reg(init=UInt(0, log2Up(mifDataBeats)))
+  val adone = io.narrow.req.valid && recv_cnt === UInt((abits-1)/w)
+  val ddone = io.narrow.req.valid && recv_cnt === UInt((dbits-1)/w)
+  val rdone = io.narrow.resp.valid && recv_cnt === UInt((rbits-1)/w)
+
+  val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(UInt(), 5)
+  val state = Reg(init=s_cmd_recv)
+
+  val in_buf = Reg(Bits())
+  when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) {
+    recv_cnt := recv_cnt + UInt(1)
+    in_buf := Cat(io.narrow.req.bits, in_buf((rbits+w-1)/w*w-1,w))
+  }
+  io.narrow.req.ready := state === s_cmd_recv || state === s_data_recv
+
+  when (state === s_cmd_recv && adone) {
+    state := s_cmd
+    recv_cnt := UInt(0)
+  }
+  when (state === s_cmd && io.wide.req_cmd.ready) {
+    state := Mux(io.wide.req_cmd.bits.rw, s_data_recv, s_reply)
+  }
+  when (state === s_data_recv && ddone) {
+    state := s_data
+    recv_cnt := UInt(0)
+  }
+  when (state === s_data && io.wide.req_data.ready) {
+    state := s_data_recv
+    when (data_recv_cnt === UInt(mifDataBeats-1)) {
+      state := s_cmd_recv
+    }
+    data_recv_cnt := data_recv_cnt + UInt(1)
+  }
+  when (rdone) { // state === s_reply
+    when (data_recv_cnt === UInt(mifDataBeats-1)) {
+      state := s_cmd_recv
+    }
+    recv_cnt := UInt(0)
+    data_recv_cnt := data_recv_cnt + UInt(1)
+  }
+
+  val req_cmd = in_buf >> UInt(((rbits+w-1)/w - (abits+w-1)/w)*w)
+  io.wide.req_cmd.valid := state === s_cmd
+  io.wide.req_cmd.bits := io.wide.req_cmd.bits.fromBits(req_cmd)
+
+  io.wide.req_data.valid := state === s_data
+  io.wide.req_data.bits.data := in_buf >> UInt(((rbits+w-1)/w - (dbits+w-1)/w)*w)
+
+  val dataq = Module(new Queue(new MemResp, mifDataBeats))
+  dataq.io.enq <> io.wide.resp
+  dataq.io.deq.ready := recv_cnt === UInt((rbits-1)/w)
+
+  io.narrow.resp.valid := dataq.io.deq.valid
+  io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UInt(w))
+}
+
+class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
+{
+  val io = new QueueIO(data, entries)
+  require(entries > 1)
+
+  val do_flow = Wire(Bool())
+  val do_enq = io.enq.fire() && !do_flow
+  val do_deq = io.deq.fire() && !do_flow
+
+  val maybe_full = Reg(init=Bool(false))
+  val enq_ptr = Counter(do_enq, entries)._1
+  val (deq_ptr, deq_done) = Counter(do_deq, entries)
+  when (do_enq != do_deq) { maybe_full := do_enq }
+
+  val ptr_match = enq_ptr === deq_ptr
+  val empty = ptr_match && !maybe_full
+  val full = ptr_match && maybe_full
+  val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
+  do_flow := empty && io.deq.ready
+
+  val ram = SeqMem(data, entries)
+  when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
+
+  val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
+  val raddr = Mux(io.deq.valid, Mux(deq_done, UInt(0), deq_ptr + UInt(1)), deq_ptr)
+  val ram_out_valid = Reg(next = ren)
+
+  io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
+  io.enq.ready := !full
+  io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren))
+}
+
+class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module
+{
+  val io = new QueueIO(data, entries)
+
+  val fq = Module(new HellaFlowQueue(entries)(data))
+  io.enq <> fq.io.enq
+  io.deq <> Queue(fq.io.deq, 1, pipe = true)
+}
+
+object HellaQueue
+{
+  def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = {
+    val q = Module((new HellaQueue(entries)) { enq.bits })
+    q.io.enq.valid := enq.valid // not using <> so that override is allowed
+    q.io.enq.bits := enq.bits
+    enq.ready := q.io.enq.ready
+    q.io.deq
+  }
+}
+
+class MemIOArbiter(val arbN: Int) extends MIFModule {
+  val io = new Bundle {
+    val inner = Vec.fill(arbN){new MemIO}.flip
+    val outer = new MemIO
+  }
+
+  if(arbN > 1) {
+    val cmd_arb = Module(new RRArbiter(new MemReqCmd, arbN))
+    val choice_q = Module(new Queue(cmd_arb.io.chosen, 4))
+    val (data_cnt, data_done) = Counter(io.outer.req_data.fire(), mifDataBeats)
+
+    io.inner.map(_.req_cmd).zipWithIndex.zip(cmd_arb.io.in).map{ case ((req, id), arb) => {
+      arb.valid := req.valid
+      arb.bits := req.bits
+      arb.bits.tag := Cat(req.bits.tag, UInt(id))
+      req.ready := arb.ready
+    }}
+    io.outer.req_cmd.bits := cmd_arb.io.out.bits
+    io.outer.req_cmd.valid := cmd_arb.io.out.valid && choice_q.io.enq.ready
+    cmd_arb.io.out.ready := io.outer.req_cmd.ready && choice_q.io.enq.ready
+    choice_q.io.enq.bits := cmd_arb.io.chosen
+    choice_q.io.enq.valid := cmd_arb.io.out.fire() && cmd_arb.io.out.bits.rw
+
+    io.outer.req_data.bits := io.inner(choice_q.io.deq.bits).req_data.bits
+    io.outer.req_data.valid := io.inner(choice_q.io.deq.bits).req_data.valid && choice_q.io.deq.valid
+    io.inner.map(_.req_data.ready).zipWithIndex.foreach {
+      case(r, i) => r := UInt(i) === choice_q.io.deq.bits && choice_q.io.deq.valid
+    }
+    choice_q.io.deq.ready := data_done
+
+    io.outer.resp.ready := Bool(false)
+    for (i <- 0 until arbN) {
+      io.inner(i).resp.valid := Bool(false)
+      when(io.outer.resp.bits.tag(log2Up(arbN)-1,0).toUInt === UInt(i)) {
+        io.inner(i).resp.valid := io.outer.resp.valid
+        io.outer.resp.ready := io.inner(i).resp.ready
+      }
+      io.inner(i).resp.bits := io.outer.resp.bits
+      io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN))
+    }
+  } else { io.inner.head <> io.outer }
+}
+
+object MemIOMemPipeIOConverter {
+  def apply(in: MemPipeIO): MemIO = {
+    val out = Wire(new MemIO())
+    in.resp.valid := out.resp.valid
+    in.resp.bits := out.resp.bits
+    out.resp.ready := Bool(true)
+    out.req_cmd.valid := in.req_cmd.valid
+    out.req_cmd.bits := in.req_cmd.bits
+    in.req_cmd.ready := out.req_cmd.ready
+    out.req_data.valid := in.req_data.valid
+    out.req_data.bits := in.req_data.bits
+    in.req_data.ready := out.req_data.ready
+    out
+  }
+}
+
+class MemPipeIOMemIOConverter(numRequests: Int) extends MIFModule {
+  val io = new Bundle {
+    val cpu = new MemIO().flip
+    val mem = new MemPipeIO
+  }
+
+  val numEntries = numRequests * mifDataBeats
+  val size = log2Down(numEntries) + 1
+
+  val inc = Wire(Bool())
+  val dec = Wire(Bool())
+  val count = Reg(init=UInt(numEntries, size))
+  val watermark = count >= UInt(mifDataBeats)
+
+  when (inc && !dec) {
+    count := count + UInt(1)
+  }
+  when (!inc && dec) {
+    count := count - UInt(mifDataBeats)
+  }
+  when (inc && dec) {
+    count := count - UInt(mifDataBeats-1)
+  }
+
+  val cmdq_mask = io.cpu.req_cmd.bits.rw || watermark
+
+  io.mem.req_cmd.valid := io.cpu.req_cmd.valid && cmdq_mask
+  io.cpu.req_cmd.ready := io.mem.req_cmd.ready && cmdq_mask
+  io.mem.req_cmd.bits := io.cpu.req_cmd.bits
+
+  io.mem.req_data <> io.cpu.req_data
+
+  // Have separate queues to allow for different mem implementations
+  val resp_data_q = Module((new HellaQueue(numEntries)) { new MemData })
+  resp_data_q.io.enq.valid := io.mem.resp.valid
+  resp_data_q.io.enq.bits.data := io.mem.resp.bits.data
+
+  val resp_tag_q = Module((new HellaQueue(numEntries)) { new MemTag })
+  resp_tag_q.io.enq.valid := io.mem.resp.valid
+  resp_tag_q.io.enq.bits.tag := io.mem.resp.bits.tag
+
+  io.cpu.resp.valid := resp_data_q.io.deq.valid && resp_tag_q.io.deq.valid
+  io.cpu.resp.bits.data := resp_data_q.io.deq.bits.data
+  io.cpu.resp.bits.tag := resp_tag_q.io.deq.bits.tag
+  resp_data_q.io.deq.ready := io.cpu.resp.ready
+  resp_tag_q.io.deq.ready := io.cpu.resp.ready
+
+  inc := resp_data_q.io.deq.fire() && resp_tag_q.io.deq.fire()
+  dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
+}

junctions/src/main/scala/nasti.scala

@@ -0,0 +1,141 @@
+// See LICENSE for license details.
+
+package junctions
+import Chisel._
+import scala.math.max
+
+case object NASTIDataBits extends Field[Int]
+case object NASTIAddrBits extends Field[Int]
+case object NASTIIdBits extends Field[Int]
+
+trait NASTIParameters extends UsesParameters {
+  val nastiXDataBits = params(NASTIDataBits)
+  val nastiWStrobeBits = nastiXDataBits / 8
+  val nastiXAddrBits = params(NASTIAddrBits)
+  val nastiWIdBits = params(NASTIIdBits)
+  val nastiRIdBits = params(NASTIIdBits)
+  val nastiXIdBits = max(nastiWIdBits, nastiRIdBits)
+  val nastiXUserBits = 1
+  val nastiAWUserBits = nastiXUserBits
+  val nastiWUserBits = nastiXUserBits
+  val nastiBUserBits = nastiXUserBits
+  val nastiARUserBits = nastiXUserBits
+  val nastiRUserBits = nastiXUserBits
+  val nastiXLenBits = 8
+  val nastiXSizeBits = 3
+  val nastiXBurstBits = 2
+  val nastiXCacheBits = 4
+  val nastiXProtBits = 3
+  val nastiXQosBits = 4
+  val nastiXRegionBits = 4
+  val nastiXRespBits = 2
+
+  def bytesToXSize(bytes: UInt) = MuxLookup(bytes, UInt("b111"), Array(
+    UInt(1) -> UInt(0),
+    UInt(2) -> UInt(1),
+    UInt(4) -> UInt(2),
+    UInt(8) -> UInt(3),
+    UInt(16) -> UInt(4),
+    UInt(32) -> UInt(5),
+    UInt(64) -> UInt(6),
+    UInt(128) -> UInt(7)))
+}
+
+abstract class NASTIBundle extends Bundle with NASTIParameters
+abstract class NASTIModule extends Module with NASTIParameters
+
+trait NASTIChannel extends NASTIBundle
+trait NASTIMasterToSlaveChannel extends NASTIChannel
+trait NASTISlaveToMasterChannel extends NASTIChannel
+
+class NASTIMasterIO extends Bundle {
+  val aw = Decoupled(new NASTIWriteAddressChannel)
+  val w  = Decoupled(new NASTIWriteDataChannel)
+  val b  = Decoupled(new NASTIWriteResponseChannel).flip
+  val ar = Decoupled(new NASTIReadAddressChannel)
+  val r  = Decoupled(new NASTIReadDataChannel).flip
+}
+
+class NASTISlaveIO extends NASTIMasterIO { flip() }
+
+trait HasNASTIMetadata extends NASTIBundle {
+  val addr   = UInt(width = nastiXAddrBits)
+  val len    = UInt(width = nastiXLenBits)
+  val size   = UInt(width = nastiXSizeBits)
+  val burst  = UInt(width = nastiXBurstBits)
+  val lock   = Bool()
+  val cache  = UInt(width = nastiXCacheBits)
+  val prot   = UInt(width = nastiXProtBits)
+  val qos    = UInt(width = nastiXQosBits)
+  val region = UInt(width = nastiXRegionBits)
+}
+
+trait HasNASTIData extends NASTIBundle {
+  val data = UInt(width = nastiXDataBits)
+  val last = Bool()
+}
+
+class NASTIAddressChannel extends NASTIMasterToSlaveChannel with HasNASTIMetadata
+
+class NASTIResponseChannel extends NASTISlaveToMasterChannel {
+  val resp = UInt(width = nastiXRespBits)
+}
+
+class NASTIWriteAddressChannel extends NASTIAddressChannel {
+  val id   = UInt(width = nastiWIdBits)
+  val user = UInt(width = nastiAWUserBits)
+}
+
+class NASTIWriteDataChannel extends NASTIMasterToSlaveChannel with HasNASTIData {
+  val strb = UInt(width = nastiWStrobeBits)
+  val user = UInt(width = nastiWUserBits)
+}
+
+class NASTIWriteResponseChannel extends NASTIResponseChannel {
+  val id   = UInt(width = nastiWIdBits)
+  val user = UInt(width = nastiBUserBits)
+}
+
+class NASTIReadAddressChannel extends NASTIAddressChannel {
+  val id   = UInt(width = nastiRIdBits)
+  val user = UInt(width = nastiARUserBits)
+}
+
+class NASTIReadDataChannel extends NASTIResponseChannel with HasNASTIData {
+  val id   = UInt(width = nastiRIdBits)
+  val user = UInt(width = nastiRUserBits)
+}
+
+class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
+  val io = new Bundle {
+    val nasti = new NASTISlaveIO
+    val mem = new MemIO
+  }
+
+  require(mifDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree")
+  val (mif_cnt_out, mif_wrap_out) = Counter(io.mem.resp.fire(), mifDataBeats)
+  
+  io.mem.req_cmd.bits.addr := Mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) >>
+                                UInt(cacheBlockOffsetBits)
+  io.mem.req_cmd.bits.tag := Mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id)
+  io.mem.req_cmd.bits.rw := io.nasti.aw.valid
+  io.mem.req_cmd.valid := (io.nasti.aw.valid && io.nasti.b.ready) || io.nasti.ar.valid
+  io.nasti.ar.ready := io.mem.req_cmd.ready && !io.nasti.aw.valid
+  io.nasti.aw.ready := io.mem.req_cmd.ready && io.nasti.b.ready
+
+  io.nasti.b.valid := io.nasti.aw.valid && io.mem.req_cmd.ready
+  io.nasti.b.bits.id := io.nasti.aw.bits.id
+  io.nasti.b.bits.resp := UInt(0)
+
+  io.nasti.w.ready := io.mem.req_data.ready
+  io.mem.req_data.valid := io.nasti.w.valid
+  io.mem.req_data.bits.data := io.nasti.w.bits.data
+  assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR, "MemIO must write full cache line")
+
+  io.nasti.r.valid := io.mem.resp.valid
+  io.nasti.r.bits.data := io.mem.resp.bits.data
+  io.nasti.r.bits.last := mif_wrap_out
+  io.nasti.r.bits.id := io.mem.resp.bits.tag
+  io.nasti.r.bits.resp := UInt(0)
+  io.mem.resp.ready := io.nasti.r.ready
+}

junctions/src/main/scala/package.scala

@@ -0,0 +1 @@
+package object junctions extends HASTIConstants with POCIConstants

junctions/src/main/scala/poci.scala

@@ -0,0 +1,88 @@
+package junctions
+
+import Chisel._
+
+abstract trait POCIConstants
+{
+  val SZ_PADDR = 32
+  val SZ_PDATA = 32
+}
+
+class POCIIO extends Bundle
+{
+  val paddr = UInt(OUTPUT, SZ_PADDR)
+  val pwrite = Bool(OUTPUT)
+  val psel = Bool(OUTPUT)
+  val penable = Bool(OUTPUT)
+  val pwdata = UInt(OUTPUT, SZ_PDATA)
+  val prdata = UInt(INPUT, SZ_PDATA)
+  val pready = Bool(INPUT)
+  val pslverr = Bool(INPUT)
+}
+
+class HASTItoPOCIBridge extends Module
+{
+  val io = new Bundle {
+    val in = new HASTISlaveIO
+    val out = new POCIIO
+  }
+
+  val s_idle :: s_setup :: s_access :: Nil = Enum(UInt(), 3)
+  val state = Reg(init = s_idle)
+  val transfer = io.in.hsel & io.in.hreadyin & io.in.htrans(1)
+
+  switch (state) {
+    is (s_idle) {
+      when (transfer) { state := s_setup }
+    }
+    is (s_setup) {
+      state := s_access
+    }
+    is (s_access) {
+      when (io.out.pready & ~transfer) { state := s_idle   }
+      when (io.out.pready & transfer)  { state := s_setup  }
+      when (~io.out.pready)            { state := s_access }
+    }
+  }
+
+  val haddr_reg = Reg(UInt(width = SZ_PADDR))
+  val hwrite_reg = Reg(UInt(width = 1))
+  when (transfer) {
+    haddr_reg  := io.in.haddr
+    hwrite_reg := io.in.hwrite
+  }
+
+  io.out.paddr := haddr_reg
+  io.out.pwrite := hwrite_reg(0)
+  io.out.psel := (state != s_idle)
+  io.out.penable := (state === s_access)
+  io.out.pwdata := io.in.hwdata
+  io.in.hrdata := io.out.prdata
+  io.in.hreadyout := ((state === s_access) & io.out.pready) | (state === s_idle)
+  io.in.hresp := io.out.pslverr
+}
+
+class POCIBus(amap: Seq[UInt=>Bool]) extends Module
+{
+  val io = new Bundle {
+    val master = new POCIIO().flip
+    val slaves = Vec.fill(amap.size){new POCIIO}
+  }
+
+  val psels = PriorityEncoderOH(
+    (io.slaves zip amap) map { case (s, afn) => {
+      s.paddr := io.master.paddr
+      s.pwrite := io.master.pwrite
+      s.pwdata := io.master.pwdata
+      afn(io.master.paddr) && io.master.psel
+  }})
+
+  (io.slaves zip psels) foreach { case (s, psel) => {
+    s.psel := psel
+    s.penable := io.master.penable && psel
+  } }
+
+  io.master.prdata := Mux1H(psels, io.slaves.map(_.prdata))
+  io.master.pready := Mux1H(psels, io.slaves.map(_.pready))
+  io.master.pslverr := Mux1H(psels, io.slaves.map(_.pslverr))
+}

junctions/src/main/scala/slowio.scala

@@ -0,0 +1,70 @@
+// See LICENSE for license details.
+
+package junctions
+import Chisel._
+
+class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
+{
+  val io = new Bundle {
+    val out_fast = Decoupled(data).flip
+    val out_slow = Decoupled(data)
+    val in_fast = Decoupled(data)
+    val in_slow = Decoupled(data).flip
+    val clk_slow = Bool(OUTPUT)
+    val set_divisor = Valid(Bits(width = 32)).flip
+    val divisor = Bits(OUTPUT, 32)
+  }
+
+  require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max))
+  val divisor = Reg(init=UInt(divisor_max-1))
+  val d_shadow = Reg(init=UInt(divisor_max-1))
+  val hold = Reg(init=UInt(divisor_max/4-1))
+  val h_shadow = Reg(init=UInt(divisor_max/4-1))
+  when (io.set_divisor.valid) {
+    d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt
+    h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt
+  }
+  io.divisor := hold << UInt(16) | divisor
+
+  val count = Reg{UInt(width = log2Up(divisor_max))}
+  val myclock = Reg{Bool()}
+  count := count + UInt(1)
+
+  val rising = count === (divisor >> UInt(1))
+  val falling = count === divisor
+  val held = count === (divisor >> UInt(1)) + hold
+
+  when (falling) {
+    divisor := d_shadow
+    hold := h_shadow
+    count := UInt(0)
+    myclock := Bool(false)
+  }
+  when (rising) {
+    myclock := Bool(true)
+  }
+
+  val in_slow_rdy = Reg(init=Bool(false))
+  val out_slow_val = Reg(init=Bool(false))
+  val out_slow_bits = Reg(data)
+
+  val fromhost_q = Module(new Queue(data,1))
+  fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset)
+  fromhost_q.io.enq.bits := io.in_slow.bits
+  fromhost_q.io.deq <> io.in_fast
+
+  val tohost_q = Module(new Queue(data,1))
+  tohost_q.io.enq <> io.out_fast
+  tohost_q.io.deq.ready := rising && io.out_slow.ready && out_slow_val
+
+  when (held) {
+    in_slow_rdy := fromhost_q.io.enq.ready
+    out_slow_val := tohost_q.io.deq.valid
+    out_slow_bits := Mux(this.reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
+  }
+
+  io.in_slow.ready := in_slow_rdy
+  io.out_slow.valid := out_slow_val
+  io.out_slow.bits := out_slow_bits
+  io.clk_slow := myclock
+}