Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
This commit is contained in:
3
.gitmodules
vendored
3
.gitmodules
vendored
@ -22,3 +22,6 @@
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[submodule "zscale"]
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path = zscale
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url = https://github.com/ucb-bar/zscale
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[submodule "junctions"]
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path = junctions
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url = https://github.com/ucb-bar/junctions
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3
Makefrag
3
Makefrag
@ -14,7 +14,8 @@ SHELL := /bin/bash
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CHISEL_ARGS := $(MODEL) --W0W --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
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src_path = src/main/scala
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chisel_srcs = $(base_dir)/$(src_path)/*.scala $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/zscale/$(src_path)/*.scala $(SRC_EXTENSION)
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default_submodules = . junctions uncore hardfloat rocket zscale
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chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules)))
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disasm := 2>
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which_disasm := $(shell which spike-dasm)
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2
chisel
2
chisel
Submodule chisel updated: cc51775dda...8ae531312f
Submodule hardfloat updated: e2e06ff615...2f5eebd75f
1
junctions
Submodule
1
junctions
Submodule
Submodule junctions added at 6152b1863e
@ -17,8 +17,9 @@ object BuildSettings extends Build {
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lazy val chisel = project
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lazy val hardfloat = project.dependsOn(chisel)
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lazy val uncore = project.dependsOn(hardfloat)
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lazy val rocket = project.dependsOn(uncore)
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lazy val junctions = project.dependsOn(chisel)
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lazy val uncore = project.dependsOn(junctions)
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lazy val rocket = project.dependsOn(hardfloat,uncore)
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lazy val zscale = project.dependsOn(rocket)
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lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale)
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2
rocket
2
rocket
Submodule rocket updated: d819fb28c3...0eefb35b2e
@ -3,6 +3,7 @@
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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@ -3,6 +3,7 @@
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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@ -192,7 +193,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
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} else {
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val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
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val conv1 = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams)
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val conv2 = Module(new MemIONASTISlaveIOConverter)
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val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
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val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
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arb.io.clients <> banks.map(_.outerTL)
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conv1.io.tl <> arb.io.managers.head
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@ -206,6 +207,6 @@ class OuterMemorySystem extends Module with TopLevelParameters {
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels)
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VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels, params(HTIFWidth))
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} else { io.mem <> mem_channels }
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}
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@ -66,7 +66,7 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets)
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} else { "\n" }
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}
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val f = createOutputFile(s"${Driver.topComponent.name}.${Driver.chiselConfigClassName.get}.d")
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val f = createOutputFile(s"${Driver.topComponent.get.name}.${Driver.chiselConfigClassName.get}.d")
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f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n"))
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f.close
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}
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@ -3,6 +3,7 @@
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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class MemDessert extends Module {
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@ -18,9 +19,10 @@ object VLSIUtils {
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mems: Seq[MemIO],
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backup: MemSerializedIO,
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en: Bool,
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nMemChannels: Int) {
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nMemChannels: Int,
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htifWidth: Int) {
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val arb = Module(new MemIOArbiter(nMemChannels))
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val mem_serdes = Module(new MemSerdes)
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val mem_serdes = Module(new MemSerdes(htifWidth))
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mem_serdes.io.wide <> arb.io.outer
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mem_serdes.io.narrow <> backup
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@ -3,6 +3,7 @@
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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import rocket._
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import zscale._
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2
uncore
2
uncore
Submodule uncore updated: 9da933836e...1ea793c040
2
zscale
2
zscale
Submodule zscale updated: 1d2c1ef49b...bde94d4e73
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