riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 213c1a4c81 fix fdiv/fsqrt control bug in fpu Yunsup Lee 2015-11-14 16:43:15 -0800
  • 4dd097d156 Merge remote-tracking branch 'origin/master' into rocc-fpu-port Yunsup Lee 2015-11-14 14:52:13 -0800
  • 6a6371fdb6 move to new version of hardfloat Yunsup Lee 2015-11-14 14:50:13 -0800
  • 3c3c946755 move to new version of hardfloat Yunsup Lee 2015-11-14 14:49:17 -0800
  • e12efab423 skip meta_write state if no meta write pending Howard Mao 2015-11-13 13:50:35 -0800
  • 608e4b2851 Merge remote-tracking branch 'origin/master' into rocc-fpu-port Yunsup Lee 2015-11-12 20:44:25 -0800
  • a1063bad54 fix issues with non-allocating put/get Howard Mao 2015-11-12 15:53:35 -0800
  • 19daee10f0 use default constructors for IOMSHR acquire construction Howard Mao 2015-11-12 11:40:40 -0800
  • 7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory Howard Mao 2015-11-12 15:40:58 -0800
  • b3865c370a make sure correct addr_beat is sent for Get response by narrower/converter Howard Mao 2015-11-12 15:40:38 -0800
  • f397d61033 add alloc option to Put constructor Howard Mao 2015-11-12 11:39:59 -0800
  • 7733fbe6a3 make sure no-alloc write still updates data array if there is a cache hit Howard Mao 2015-11-12 11:39:36 -0800
  • 10f4c6c71c interleave cached and uncached requests Howard Mao 2015-11-12 11:34:44 -0800
  • 97d0e195ae Merge pull request #28 from ucb-bar/yusnup Colin Schmidt 2015-11-12 00:46:21 -0800
  • 07f0e6be94 Don't re-generate the .d files on "make clean" Palmer Dabbelt 2015-11-12 00:41:55 -0800
  • 7cae6cedf5 finished bit should be set true if generator not being used Howard Mao 2015-11-11 18:51:16 -0800
  • f93872d6b4 make sure cached generator actually drives finished signal Howard Mao 2015-11-11 18:45:36 -0800
  • eeda3dd770 add README Howard Mao 2015-11-11 18:30:19 -0800
  • 9482d944ca make Uncached generator vary the alloc bit Howard Mao 2015-11-11 18:26:56 -0800
  • 6ddf81090b didn't mean to turn off GenerateCached in last commit Howard Mao 2015-11-11 17:39:08 -0800
  • 11f0b3d8db restore old L2 cache AcquireTransactor configuration Howard Mao 2015-11-11 17:10:58 -0800
  • 31da692ccc default to single tile in WithMemtest Howard Mao 2015-11-11 14:54:13 -0800
  • 55581195eb add groundtest submodule for simple memory testing Howard Mao 2015-11-10 13:39:08 -0800
  • 8a6b231b08 explicitly configure the number of requests being sent by generators Howard Mao 2015-11-11 14:32:19 -0800
  • 149480411e make sure ClientTileLinkEnqueuer uses the correct parameters Howard Mao 2015-11-10 16:09:19 -0800
  • b59ce5fed4 make sure L2 waits for outer grant before sending grant for write request Howard Mao 2015-11-10 16:06:14 -0800
  • 13f62e0364 make sure generators can detect lockup Howard Mao 2015-11-10 14:39:56 -0800
  • 520925c207 fix up build.sbt and add gitignore Howard Mao 2015-11-10 13:38:39 -0800
  • 51f128ec74 actually use backendBuffering in front of unwrapper/converter chain Howard Mao 2015-11-09 11:50:08 -0800
  • 42d3d09d7a add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer Howard Mao 2015-11-09 11:49:19 -0800
  • 7942be4e01 make sure outerTL method is idempotent Howard Mao 2015-11-09 11:10:02 -0800
  • 59ca373146 Merge pull request #18 from jackkoenig/master Andrew Waterman 2015-11-08 22:38:01 -0800
  • 1e259a55da Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later jackkoenig 2015-11-08 21:16:31 -0800
  • df5daaa72e Merge remote-tracking branch 'origin/master' into rocc-fpu-port Yunsup Lee 2015-11-06 23:57:42 -0800
  • 2f515b2af6 Reduce critical path for fdiv valid signal Andrew Waterman 2015-11-06 23:25:33 -0800
  • e3efc09b5b remove unnecessary UInt encode/decode on releaseMatches path Henry Cook 2015-11-05 17:20:03 -0800
  • 1e772daeea no spaces in Makefrag Yunsup Lee 2015-11-05 16:42:05 -0800
  • cb0c2df051 update fpga-zynq Howard Mao 2015-11-05 10:50:13 -0800
  • 42e7067400 bump uncore Howard Mao 2015-11-05 10:49:25 -0800
  • bbf14ddc01 use definitions in consts header whenever possible Howard Mao 2015-11-05 10:15:02 -0800
  • fb501e75c0 fixes for sub-block TL requests in uncore Howard Mao 2015-11-02 22:52:39 -0800
  • 7b252d8f89 get rid of now-unnecessary bits in MIF tag Howard Mao 2015-11-02 22:51:20 -0800
  • ba5a6af05c correctly stripe data across memory channels in simulation Howard Mao 2015-11-02 22:46:52 -0800
  • ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity Sagar Karandikar 2015-11-04 23:18:34 -0800
  • 354abf5e6b fix NSets calculation Sagar Karandikar 2015-11-04 22:15:47 -0800
  • dcef020ca0 get multichannel simulation working in emulator Howard Mao 2015-11-02 20:10:10 -0800
  • 04d92dddbd add back decoupled NASTI connection at edge of RocketChip Howard Mao 2015-11-02 17:01:28 -0800
  • 51116e0674 add 2 and 4 memory channel configs Yunsup Lee 2015-10-31 00:00:09 -0700
  • 0d245741bc add multichannel NASTI support in Verilog testbench Yunsup Lee 2015-10-30 21:14:33 -0700
  • 9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout Howard Mao 2015-10-14 11:33:18 -0700
  • 3698153535 OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank Henry Cook 2015-11-03 14:31:35 -0800
  • 3e906c8620 shave off channel select bits in MultiChannel router Howard Mao 2015-11-02 22:39:50 -0800
  • baa2544651 Fix some more issues with narrower Howard Mao 2015-10-31 18:56:17 -0700
  • d844bee310 properly shift grant data when checking correctness Howard Mao 2015-10-31 18:58:05 -0700
  • 644b66a3a8 selectively enable or disable uncached and cached generators Howard Mao 2015-10-31 17:43:25 -0700
  • bcc631f756 generate word-size requests in uncached generator Howard Mao 2015-10-31 17:43:08 -0700
  • 812c5bcc55 make sure narrower can handle sub-block level requests correctly Howard Mao 2015-10-31 15:58:36 -0700
  • d4b8653002 fix too strict assertion in broadcast hub Howard Mao 2015-10-31 15:58:10 -0700
  • c1f42ce3d4 add an L1 cache request generator Howard Mao 2015-10-30 12:49:57 -0700
  • 032bdd0601 Merge pull request #24 from ucb-bar/regression-master Colin Schmidt 2015-10-29 14:15:44 -0700
  • 3d2a4ffdd6 Add a "--master" flag to the regression script Palmer Dabbelt 2015-10-29 14:11:26 -0700
  • 3103fa8da2 rename tl to mem in generator Howard Mao 2015-10-27 16:42:31 -0700
  • c10870a87c make sure ID width requirement in TL -> NASTI converter is correct Howard Mao 2015-10-27 13:25:29 -0700
  • aeb9c86459 use the uncached port instead of the cached port Howard Mao 2015-10-26 23:09:36 -0700
  • b22088d934 make sure data checked is same as data sent Howard Mao 2015-10-26 21:55:04 -0700
  • 2b252bc6ff first commit Howard Mao 2015-10-26 21:37:35 -0700
  • 86d67051b2 Merge commit 'e31be75' into rocc-fpu-port Colin Schmidt 2015-10-26 16:29:51 -0700
  • eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect Howard Mao 2015-10-26 14:11:49 -0700
  • f37938e4de implement MultiChannel routing Howard Mao 2015-10-26 12:30:47 -0700
  • 096dbb3c2d get rid of NastiTopInterconnect Howard Mao 2015-10-26 14:14:53 -0700
  • 5440d6c2ae balance MultiChannel router correctly Howard Mao 2015-10-26 12:23:03 -0700
  • 9fa4541916 get rid of unused full signal in ReorderQueue Howard Mao 2015-10-26 12:17:25 -0700
  • 3270d17ad3 add MultiChannel routing to Nasti interconnect generator Howard Mao 2015-10-23 16:25:17 -0700
  • a175afae73 make ZscaleChip work with new parameters framework Yunsup Lee 2015-10-25 10:24:39 -0700
  • c7235fecb5 further state optimization in CSRfile when not UseVM Yunsup Lee 2015-10-25 10:23:46 -0700
  • c3a7dcf0ab fix missing cde library dependencies in submodules Howard Mao 2015-10-23 15:05:19 -0700
  • 854feab08e add knob and constraint dumping Colin Schmidt 2015-10-22 17:25:38 -0700
  • 652fb393a3 Merge remote-tracking branch 'origin/master' into rocc-fpu-port Colin Schmidt 2015-10-22 16:38:28 -0700
  • 6403f27fbe fix bug in ReorderQueue breaking TileLink Unwrapper Howard Mao 2015-10-22 15:51:40 -0700
  • 0c587704a7 Add ability to generate libraryDependency on cde. Jim Lawson 2015-10-22 11:37:20 -0700
  • 4c2b0a9032 Add ability to generate libraryDependency on cde. Jim Lawson 2015-10-22 09:57:02 -0700
  • 8fe4917d8e Add ability to generate libraryDependency on cde. Jim Lawson 2015-10-22 09:52:26 -0700
  • 9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) Henry Cook 2015-10-21 18:23:58 -0700
  • 47bc193c16 added CDE library as submodule Henry Cook 2015-10-20 16:22:07 -0700
  • 4f8468b60f depend on external cde library Henry Cook 2015-10-21 18:18:32 -0700
  • f8594da1d3 depend on external cde library Henry Cook 2015-10-21 18:16:44 -0700
  • 9c3cd8f9fe depend on external cde library Henry Cook 2015-10-21 18:15:46 -0700
  • 942f6a7d7f Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port Colin Schmidt 2015-10-21 12:03:10 -0700
  • 21f342ad42 fix typo causing L2 cache configuration to fail Howard Mao 2015-10-21 13:37:33 -0700
  • 97f29b1618 Merge remote-tracking branch 'origin/master' into rocc-fpu-port Colin Schmidt 2015-10-20 19:05:10 -0700
  • 02d113b39f outerDataBits / innerDataBits should be per beat, not per block Howard Mao 2015-10-21 11:31:13 -0700
  • d5a75fd113 accidentally committed some code I didn't mean to in Rocket Howard Mao 2015-10-21 09:21:54 -0700
  • 0b7c828b5d go back to using standard LockingArbiter Howard Mao 2015-10-21 09:15:51 -0700
  • 693a4ae00e fix some more memory system bugs Howard Mao 2015-10-20 23:29:59 -0700
  • baf95533a4 fix combinational loop in TileLink Unwrapper Howard Mao 2015-10-20 23:26:11 -0700
  • c68d9f8137 make ProbeUnit state machine easier to understand Howard Mao 2015-10-20 23:25:23 -0700
  • ffe7df2fed make sure TL -> NASTI converter acquire ready not dependent on valid Howard Mao 2015-10-19 22:46:03 -0700
  • c311c9938e nitpicky declaration move Howard Mao 2015-10-20 21:10:54 -0700
  • 1c135c1628 fix ready-valid mixup in TileLink unwrapper Howard Mao 2015-10-19 17:25:33 -0700
  • 62765e9609 L2 rowBits param bugfix Henry Cook 2015-10-20 18:56:22 -0700