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10
groundtest/build.sbt
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10
groundtest/build.sbt
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organization := "edu.berkeley.cs"
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version := "1.2"
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name := "groundtest"
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scalaVersion := "2.11.6"
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libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "rocket").map {
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dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten
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93
groundtest/src/main/scala/generator.scala
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93
groundtest/src/main/scala/generator.scala
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package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import scala.util.Random
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import cde.{Parameters, Field}
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case object BuildGenerator extends Field[(Int, Random, Parameters) => TileLinkGenerator]
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case object NGeneratorsPerTile extends Field[Int]
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case object NGeneratorTiles extends Field[Int]
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trait HasGeneratorParams {
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implicit val p: Parameters
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val nGensPerTile = p(NGeneratorsPerTile)
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val nGenTiles = p(NGeneratorTiles)
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val nGens = nGensPerTile * nGenTiles
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}
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abstract class TileLinkGenerator(rnd: Random)
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
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val io = new Bundle {
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val tl = new ClientTileLinkIO
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val finished = Bool(OUTPUT)
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}
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}
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class UncachedTileLinkGenerator(id: Int, rnd: Random)
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(implicit p: Parameters) extends TileLinkGenerator(rnd)(p) {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt
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private val totalRequests = maxAddress / nGens
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def rndDataBeat(): UInt = { UInt(BigInt(tlDataBits, rnd), tlDataBits) }
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val (acq_beat, acq_done) = Counter(io.tl.acquire.fire() && state === s_put, tlDataBeats)
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val (gnt_beat, gnt_done) = Counter(io.tl.grant.fire() && state === s_get, tlDataBeats)
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val (req_cnt, req_wrap) = Counter(gnt_done && state === s_get, totalRequests)
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val addr_block = Cat(req_cnt, UInt(id, log2Up(nGens)))
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val sending = Reg(init = Bool(false))
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when (state === s_start) {
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sending := Bool(true)
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state := s_put
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}
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when (state === s_put) {
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when (acq_done) { sending := Bool(false) }
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when (io.tl.grant.fire()) { sending := Bool(true); state := s_get }
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}
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when (state === s_get) {
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when (io.tl.acquire.fire()) { sending := Bool(false) }
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when (gnt_done) {
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sending := Bool(true)
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state := Mux(req_wrap, s_finished, s_put)
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}
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}
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io.finished := (state === s_finished)
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val full_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits))
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val put_data = Cat(UInt(id, log2Up(nGens)), req_cnt, full_addr)
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val put_acquire = PutBlock(
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client_xact_id = UInt(0),
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addr_block = addr_block,
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addr_beat = acq_beat,
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data = put_data)
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val get_acquire = GetBlock(
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client_xact_id = UInt(0),
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addr_block = addr_block)
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io.tl.acquire.valid := sending
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io.tl.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.tl.grant.ready := !sending
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assert(!io.tl.grant.valid || state != s_get ||
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io.tl.grant.bits.data === put_data,
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"Get received incorrect data")
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io.tl.release.valid := Bool(false)
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io.tl.probe.ready := Bool(false)
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assert(!io.tl.probe.valid, "Uncached generator cannot accept probes")
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}
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45
groundtest/src/main/scala/tile.scala
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45
groundtest/src/main/scala/tile.scala
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package groundtest
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import Chisel._
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import rocket._
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import uncore._
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import scala.util.Random
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import cde.Parameters
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class GeneratorTile(id: Int, rnd: Random, resetSignal: Bool)
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(implicit val p: Parameters) extends Tile(resetSignal)(p)
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with HasGeneratorParams {
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val gen_finished = Wire(Vec(nGensPerTile, Bool()))
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val arb = Module(new ClientTileLinkIOArbiter(nGensPerTile))
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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val generator = p(BuildGenerator)(genid, rnd, p)
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arb.io.in(i) <> generator.io.tl
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gen_finished(i) := generator.io.finished
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}
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io.cached(0) <> arb.io.out
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io.uncached(0).acquire.valid := Bool(false)
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io.uncached(0).grant.ready := Bool(false)
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val all_done = gen_finished.reduce(_ && _)
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val csr_resp_valid = Reg(Bool()) // Don't reset
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val csr_resp_data = Reg(io.host.csr.resp.bits)
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io.host.csr.req.ready := Bool(true)
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io.host.csr.resp.valid := csr_resp_valid
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io.host.csr.resp.bits := csr_resp_data
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when (io.host.csr.req.fire()) {
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val req = io.host.csr.req.bits
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csr_resp_valid := Bool(true)
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csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), all_done, req.data)
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}
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when (io.host.csr.resp.fire()) {
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csr_resp_valid := Bool(false)
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}
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}
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