explicitly configure the number of requests being sent by generators
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13f62e0364
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8a6b231b08
@ -11,6 +11,7 @@ case object NGeneratorsPerTile extends Field[Int]
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case object NGeneratorTiles extends Field[Int]
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case object GenerateUncached extends Field[Boolean]
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case object GenerateCached extends Field[Boolean]
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case object MaxGenerateRequests extends Field[Int]
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trait HasGeneratorParams {
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implicit val p: Parameters
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@ -20,6 +21,7 @@ trait HasGeneratorParams {
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val genUncached = p(GenerateUncached)
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val genCached = p(GenerateCached)
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val genTimeout = 4096
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val maxRequests = p(MaxGenerateRequests)
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}
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class Timer(initCount: Int) extends Module {
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@ -63,8 +65,6 @@ class UncachedTileLinkGenerator(id: Int)
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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private val wordBits = 64
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private val wordOffset = log2Up(wordBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt / 2
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private val totalRequests = maxAddress / nGens
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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@ -74,7 +74,7 @@ class UncachedTileLinkGenerator(id: Int)
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, totalRequests)
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, maxRequests)
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val sending = Reg(init = Bool(false))
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@ -147,9 +147,7 @@ class HellaCacheGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParams {
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private val wordOffset = log2Up(coreDataBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt
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private val startAddress = maxAddress / 2
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private val totalRequests = (maxAddress - startAddress) / nGens
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private val startAddress = (p(MMIOBase) >> wordOffset).toInt / 2
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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@ -164,7 +162,7 @@ class HellaCacheGenerator(id: Int)
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val sending = Reg(init = Bool(false))
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val (req_cnt, req_wrap) = Counter(
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io.mem.resp.valid && io.mem.resp.bits.has_data, totalRequests)
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io.mem.resp.valid && io.mem.resp.bits.has_data, maxRequests)
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val req_addr = UInt(startAddress) +
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Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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