make sure generators can detect lockup
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520925c207
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13f62e0364
@ -19,6 +19,42 @@ trait HasGeneratorParams {
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val nGens = nGensPerTile * nGenTiles
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val genUncached = p(GenerateUncached)
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val genCached = p(GenerateCached)
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val genTimeout = 4096
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}
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class Timer(initCount: Int) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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val stop = Bool(INPUT)
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val timeout = Bool(OUTPUT)
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}
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val countdown = Reg(UInt(width = log2Up(initCount)))
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val active = Reg(init = Bool(false))
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when (io.start) {
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countdown := UInt(initCount - 1)
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active := Bool(true)
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}
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when (io.stop) {
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active := Bool(false)
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}
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when (active) {
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countdown := countdown - UInt(1)
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}
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io.timeout := countdown === UInt(0)
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}
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object Timer {
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def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
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val timer = Module(new Timer(initCount))
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timer.io.start := start
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timer.io.stop := stop
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timer.io.timeout
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}
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}
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class UncachedTileLinkGenerator(id: Int)
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@ -60,6 +96,9 @@ class UncachedTileLinkGenerator(id: Int)
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}
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}
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val timeout = Timer(genTimeout, io.mem.acquire.fire(), io.mem.grant.fire())
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assert(!timeout, s"Uncached generator ${id} timed out waiting for grant")
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io.finished := (state === s_finished)
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val full_addr = Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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@ -117,6 +156,9 @@ class HellaCacheGenerator(id: Int)
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val mem = new HellaCacheIO
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}
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val timeout = Timer(genTimeout, io.mem.req.fire(), io.mem.resp.fire())
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assert(!timeout, s"Cached generator ${id} timed out waiting for response")
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val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val sending = Reg(init = Bool(false))
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