riscv/rocket-chip
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L2 rowBits param bugfix

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This commit is contained in:
Henry Cook 2015-10-20 18:56:22 -07:00
parent 3fc630405b
commit 62765e9609
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/Configs.scala
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@ -193,7 +193,7 @@ class WithL2Cache extends ChiselConfig(
site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
site(NWays)
case NWays => Knob("L2_WAYS")
case RowBits => site(TLKey(site(TLId))).dataBits
case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
}: PartialFunction[Any,Any]
case NAcquireTransactors => 2
case NSecondaryMisses => 4