Merge commit 'e31be75' into rocc-fpu-port
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commit
86d67051b2
@ -293,7 +293,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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io.fatc := insn_sfence_vm
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io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + MTVEC,
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Mux(maybe_insn_redirect_trap, reg_stvec.sextTo(vaddrBitsExtended),
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Mux(reg_mstatus.prv(1), reg_mepc, reg_sepc)))
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Mux(reg_mstatus.prv(1) || Bool(!p(UseVM)), reg_mepc, reg_sepc)))
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io.ptbr := reg_sptbr
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io.csr_xcpt := csr_xcpt
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io.eret := insn_ret || insn_redirect_trap
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