Merge remote-tracking branch 'origin/master' into rocc-fpu-port

rocket/build.sbt

@@ -6,5 +6,5 @@ name := "rocket"
 
 scalaVersion := "2.11.6"
 
-libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions").map {
+libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "cde").map {
   dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

rocket/src/main/scala/arbiter.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import uncore._
+import cde.{Parameters, Field}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
 {

rocket/src/main/scala/btb.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import junctions._
+import cde.{Parameters, Field}
 import Util._
 
 case object BtbKey extends Field[BtbParameters]

rocket/src/main/scala/csr.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import Util._
 import Instructions._
+import cde.{Parameters, Field}
 import uncore._
 import scala.math._
 

rocket/src/main/scala/dpath_alu.scala

@@ -3,6 +3,7 @@
 package rocket
 
 import Chisel._
+import cde.{Parameters, Field}
 import Instructions._
 
 object ALU

rocket/src/main/scala/fpu.scala

@@ -7,6 +7,7 @@ import Instructions._
 import Util._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
+import cde.{Parameters, Field}
 
 case object SFMALatency
 case object DFMALatency

rocket/src/main/scala/frontend.scala

@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)

rocket/src/main/scala/icache.scala

@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats

rocket/src/main/scala/nbdcache.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import junctions._
+import cde.{Parameters, Field}
 import Util._
 
 case object WordBits extends Field[Int]

rocket/src/main/scala/ptw.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val addr = UInt(width = vpnBits)

rocket/src/main/scala/rocc.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]

rocket/src/main/scala/rocket.scala

@@ -6,6 +6,7 @@ import Chisel._
 import junctions._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object UseFPU extends Field[Boolean]
 case object FDivSqrt extends Field[Boolean]

rocket/src/main/scala/tile.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object CoreName extends Field[String]
 case object BuildRoCC extends Field[Option[Parameters => RoCC]]

rocket/src/main/scala/tlb.scala

@@ -6,6 +6,7 @@ import Chisel._
 import Util._
 import junctions._
 import scala.math._
+import cde.{Parameters, Field}
 
 case object NTLBEntries extends Field[Int]
 

rocket/src/main/scala/util.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import scala.math._
+import cde.{Parameters, Field}
 
 object Util {
   implicit def intToUInt(x: Int): UInt = UInt(x)