add an L1 cache request generator
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@ -3,6 +3,7 @@ package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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@ -20,7 +21,7 @@ class UncachedTileLinkGenerator(id: Int)
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt
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private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt / 2
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private val totalRequests = maxAddress / nGens
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val io = new Bundle {
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@ -81,6 +82,54 @@ class UncachedTileLinkGenerator(id: Int)
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assert(!io.mem.grant.valid || state != s_get ||
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io.mem.grant.bits.data === get_data,
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s"Get received incorrect data in generator ${id}")
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s"Get received incorrect data in uncached generator ${id}")
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}
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class HellaCacheGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParams {
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private val wordOffset = log2Up(coreDataBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt
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private val startAddress = maxAddress / 2
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private val totalRequests = (maxAddress - startAddress) / nGens
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new HellaCacheIO
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}
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val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val sending = Reg(init = Bool(false))
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val (req_cnt, req_wrap) = Counter(
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io.mem.resp.valid && io.mem.resp.bits.has_data, totalRequests)
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val req_addr = UInt(startAddress) +
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Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr)
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io.mem.req.valid := sending
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.data := req_data
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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io.mem.req.bits.tag := UInt(0)
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io.mem.req.bits.kill := Bool(false)
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io.mem.req.bits.phys := Bool(true)
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when (state === s_start) { sending := Bool(true); state := s_write }
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when (io.mem.req.fire()) { sending := Bool(false) }
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when (io.mem.resp.valid) {
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sending := Bool(true)
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state := Mux(state === s_write, s_read, s_write)
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}
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when (req_wrap) { sending := Bool(false); state := s_finished }
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assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
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io.mem.resp.bits.data === req_data,
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s"Received incorrect data in cached generator ${id}")
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}
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@ -36,19 +36,34 @@ class DummyCache(implicit val p: Parameters) extends Module
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class GeneratorTile(id: Int, resetSignal: Bool)
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(implicit val p: Parameters) extends Tile(resetSignal)(p)
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with HasGeneratorParams {
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val gen_finished = Wire(Vec(nGensPerTile, Bool()))
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val arb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
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val gen_finished = Wire(Vec(2 * nGensPerTile, Bool()))
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val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
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val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams))
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val cache = Module(new HellaCache()(dcacheParams))
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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val generator = Module(new UncachedTileLinkGenerator(genid))
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arb.io.in(i) <> generator.io.mem
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gen_finished(i) := generator.io.finished
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val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
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val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams))
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val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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uncacheArb.io.in(i) <> uncacheGen.io.mem
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cacheIF.io.requestor <> cacheGen.io.mem
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cacheArb.io.requestor(i) <> cacheIF.io.cache
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gen_finished(2 * i) := uncacheGen.io.finished
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gen_finished(2 * i + 1) := cacheGen.io.finished
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}
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io.uncached(0) <> arb.io.out
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io.cached(0) <> Module(new DummyCache).io
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cache.io.ptw.req.ready := Bool(false)
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cache.io.ptw.resp.valid := Bool(false)
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cache.io.cpu <> cacheArb.io.mem
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assert(!cache.io.ptw.req.valid,
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"Cache should not be using virtual addressing")
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io.uncached(0) <> uncacheArb.io.out
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io.cached(0) <> cache.io.mem
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val all_done = gen_finished.reduce(_ && _)
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