riscv/rocket-chip
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implement MultiChannel routing

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This commit is contained in:
Howard Mao 2015-10-26 12:30:47 -07:00
parent a175afae73
commit f37938e4de
3 changed files with 7 additions and 4 deletions
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2
junctions

@ -1 +1 @@
Subproject commit e8cb7b8b57c12c47b42484c0c073a031a88137a4
Subproject commit 2982167822874831b0acee4b80c3c76f54bb4417

7
src/main/scala/Configs.scala
View File

@ -41,8 +41,11 @@ class DefaultConfig extends Config (
case VAddrBits => site(VPNBits) + site(PgIdxBits)
case ASIdBits => 7
case MIFTagBits => Dump("MEM_TAG_BITS",
// Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
log2Up(site(NBanksPerMemoryChannel)) +
// Bits added by NASTI interconnect
log2Up(site(NMemoryChannels) * site(NBanksPerMemoryChannel) + 1) +
// Bits added by final arbiter (not needed if true multichannel memory)
log2Up(site(NMemoryChannels)))
case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
@ -159,7 +162,7 @@ class DefaultConfig extends Config (
case MMIOBase => BigInt(1 << 30) // 1 GB
case ExternalIOStart => 2 * site(MMIOBase)
case GlobalAddrMap => AddrMap(
AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
AddrMapEntry("mem", None, MemChannels(site(MMIOBase), site(NMemoryChannels), AddrMapConsts.RWX)),
AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
}},

2
uncore

@ -1 +1 @@
Subproject commit 411d02c5f225092577d04ef0c2719e341a5f7d93
Subproject commit c862e97f68a0968634a588194886544f95b23bc9