riscv/rocket-chip
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fix issues with non-allocating put/get

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This commit is contained in:
Howard Mao 2015-11-12 15:53:35 -08:00
parent 97d0e195ae
commit a1063bad54
4 changed files with 5 additions and 4 deletions
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2
groundtest

@ -1 +1 @@
Subproject commit 5ed7616fef03d3291123a4844565a165d2738bf8
Subproject commit cb4b70a820fc04e86b6c7e6cf8c4faed699283ce

2
rocket

@ -1 +1 @@
Subproject commit e31be75a6a6d2ff0334fc1f9ce9c4730281bd09a
Subproject commit d4939b57e0c468896d972dc11b27611e4b09e560

3
src/main/scala/Configs.scala
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@ -267,7 +267,8 @@ class WithMemtest extends Config (
case NGeneratorsPerTile => 1
case GenerateUncached => true
case GenerateCached => true
case MaxGenerateRequests => 8192
case MaxGenerateRequests => 128
case GeneratorStartAddress => 0
case BuildTiles => {
(0 until site(NTiles)).map { i =>

2
uncore

@ -1 +1 @@
Subproject commit edf24e289d162bdd697fe31342b907123e7e82dd
Subproject commit e53b5072caf12a2c18245cecd709204a4231d2d9