riscv/rocket-chip
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fix fdiv/fsqrt control bug in fpu

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This commit is contained in:
Yunsup Lee 2015-11-14 16:43:15 -08:00
parent 3c3c946755
commit 213c1a4c81
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/fpu.scala
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@ -609,7 +609,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
val divSqrt = Module(new hardfloat.DivSqrtRecF64)
divSqrt_inReady := Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
divSqrt.io.inValid := mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt)
divSqrt.io.inValid := mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_in_flight
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := fpiu.io.as_double.in1
divSqrt.io.b := fpiu.io.as_double.in2