make Uncached generator vary the alloc bit
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8a6b231b08
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@ -118,7 +118,8 @@ class UncachedTileLinkGenerator(id: Int)
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = beat_data,
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wmask = Some(wmask))
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wmask = Some(wmask),
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alloc = req_cnt(0))
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val get_acquire = Get(
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client_xact_id = UInt(0),
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@ -126,7 +127,7 @@ class UncachedTileLinkGenerator(id: Int)
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addr_beat = addr_beat,
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addr_byte = addr_byte,
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operand_size = MT_D,
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alloc = Bool(true))
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alloc = req_cnt(0))
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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