selectively enable or disable uncached and cached generators
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bcc631f756
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@ -9,12 +9,16 @@ import cde.{Parameters, Field}
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case object NGeneratorsPerTile extends Field[Int]
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case object NGeneratorTiles extends Field[Int]
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case object GenerateUncached extends Field[Boolean]
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case object GenerateCached extends Field[Boolean]
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trait HasGeneratorParams {
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implicit val p: Parameters
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val nGensPerTile = p(NGeneratorsPerTile)
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val nGenTiles = p(NGeneratorTiles)
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val nGens = nGensPerTile * nGenTiles
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val genUncached = p(GenerateUncached)
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val genCached = p(GenerateCached)
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}
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class UncachedTileLinkGenerator(id: Int)
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@ -39,31 +39,48 @@ class GeneratorTile(id: Int, resetSignal: Bool)
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val gen_finished = Wire(Vec(2 * nGensPerTile, Bool()))
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val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
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val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams))
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val cache = Module(new HellaCache()(dcacheParams))
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if (genUncached) {
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val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
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val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams))
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val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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uncacheArb.io.in(i) <> uncacheGen.io.mem
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cacheIF.io.requestor <> cacheGen.io.mem
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cacheArb.io.requestor(i) <> cacheIF.io.cache
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gen_finished(2 * i) := uncacheGen.io.finished
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gen_finished(2 * i + 1) := cacheGen.io.finished
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
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uncacheArb.io.in(i) <> uncacheGen.io.mem
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gen_finished(2 * i) := uncacheGen.io.finished
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}
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io.uncached(0) <> uncacheArb.io.out
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} else {
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io.uncached(0).acquire.valid := Bool(false)
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io.uncached(0).grant.ready := Bool(false)
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for (i <- 0 until nGensPerTile) { gen_finished(2 * i) := Bool(false) }
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}
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cache.io.ptw.req.ready := Bool(false)
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cache.io.ptw.resp.valid := Bool(false)
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cache.io.cpu <> cacheArb.io.mem
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if (genCached) {
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val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams))
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val cache = Module(new HellaCache()(dcacheParams))
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assert(!cache.io.ptw.req.valid,
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"Cache should not be using virtual addressing")
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams))
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val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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cacheIF.io.requestor <> cacheGen.io.mem
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cacheArb.io.requestor(i) <> cacheIF.io.cache
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gen_finished(2 * i + 1) := cacheGen.io.finished
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}
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io.uncached(0) <> uncacheArb.io.out
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io.cached(0) <> cache.io.mem
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cache.io.ptw.req.ready := Bool(false)
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cache.io.ptw.resp.valid := Bool(false)
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cache.io.cpu <> cacheArb.io.mem
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assert(!cache.io.ptw.req.valid,
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"Cache should not be using virtual addressing")
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io.cached(0) <> cache.io.mem
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} else {
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io.cached(0) <> Module(new DummyCache).io
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for (i <- 0 until nGensPerTile) { gen_finished(2 * i + 1) := Bool(true) }
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}
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val all_done = gen_finished.reduce(_ && _)
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