generate word-size requests in uncached generator
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@ -21,7 +21,9 @@ class UncachedTileLinkGenerator(id: Int)
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt / 2
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private val wordBits = 64
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private val wordOffset = log2Up(wordBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt / 2
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private val totalRequests = maxAddress / nGens
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val io = new Bundle {
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@ -32,11 +34,7 @@ class UncachedTileLinkGenerator(id: Int)
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val (acq_beat, acq_done) = Counter(io.mem.acquire.fire() && state === s_put, tlDataBeats)
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val (gnt_beat, gnt_done) = Counter(io.mem.grant.fire() && state === s_get, tlDataBeats)
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val (req_cnt, req_wrap) = Counter(gnt_done && state === s_get, totalRequests)
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val addr_block = Cat(req_cnt, UInt(id, log2Up(nGens)))
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, totalRequests)
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val sending = Reg(init = Bool(false))
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@ -46,13 +44,13 @@ class UncachedTileLinkGenerator(id: Int)
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}
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when (state === s_put) {
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when (acq_done) { sending := Bool(false) }
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (io.mem.grant.fire()) { sending := Bool(true); state := s_get }
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}
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when (state === s_get) {
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (gnt_done) {
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when (io.mem.grant.fire()) {
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sending := Bool(true)
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state := Mux(req_wrap, s_finished, s_put)
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}
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@ -60,28 +58,39 @@ class UncachedTileLinkGenerator(id: Int)
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io.finished := (state === s_finished)
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val acq_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits))
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val gnt_addr = Cat(addr_block, gnt_beat, UInt(0, tlByteAddrBits))
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val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
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val put_data = Cat(data_prefix, acq_addr)
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val get_data = Cat(data_prefix, gnt_addr)
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val full_addr = Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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val addr_block = full_addr >> UInt(tlBlockOffset)
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val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits)
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val addr_byte = full_addr(tlByteAddrBits - 1, 0)
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val put_acquire = PutBlock(
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val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
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val word_data = Wire(UInt(width = wordBits))
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word_data := Cat(data_prefix, full_addr)
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val beat_data = Fill(tlDataBits / wordBits, word_data)
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val wshift = Cat(full_addr(tlByteAddrBits - 1, wordOffset), UInt(0, wordOffset))
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val wmask = Fill(wordBits / 8, Bits(1, 1)) << wshift
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val put_acquire = Put(
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client_xact_id = UInt(0),
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addr_block = addr_block,
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addr_beat = acq_beat,
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data = put_data)
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addr_beat = addr_beat,
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data = beat_data,
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wmask = Some(wmask))
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val get_acquire = GetBlock(
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val get_acquire = Get(
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client_xact_id = UInt(0),
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addr_block = addr_block)
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addr_block = addr_block,
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addr_beat = addr_beat,
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addr_byte = addr_byte,
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operand_size = MT_D,
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alloc = Bool(true))
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.grant.ready := !sending
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assert(!io.mem.grant.valid || state != s_get ||
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io.mem.grant.bits.data === get_data,
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assert(!io.mem.grant.valid || state =/= s_get ||
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io.mem.grant.bits.data(63, 0) === word_data,
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s"Get received incorrect data in uncached generator ${id}")
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}
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