Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
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2f515b2af6
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@ -751,6 +751,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val s1_clk_en = Reg(Bool())
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val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
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val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
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val s2_req = Reg(io.cpu.req.bits)
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val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
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val s2_recycle = Wire(Bool())
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@ -1053,7 +1054,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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uncache_resp.bits := mshrs.io.resp.bits
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uncache_resp.valid := mshrs.io.resp.valid
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val cache_pass = s2_valid || s2_replay
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val cache_pass = s2_valid || s2_killed || s2_replay
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mshrs.io.resp.ready := !cache_pass
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io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
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