riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
1,545 Commits 1 Branch 0 Tags 13 MiB
ce242b8f3f
Commit Graph

1545 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. Terpstra
11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
mwachs5
740a6073f6 Add Debug Module (#49) 
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
 2016-06-01 16:33:33 -07:00
Howard Mao
e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
Andrew Waterman
1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Andrew Waterman
6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Howard Mao
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Andrew Waterman
391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman
b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman
8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman
22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Wesley W. Terpstra
7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Andrew Waterman
c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman
88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Wesley W. Terpstra
a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00
Albert Ou
ee0acc1d07 Fix BRAM assertion condition 2016-05-23 13:19:53 -07:00
Colin Schmidt
3e0b5d6fd9 Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release, 
but would otherwise be allocated.

Closes #45
 2016-05-20 16:35:30 -07:00
Ken McMillan
fd83d20857 Use a def instead of a lazy val in ManagerCoherenceAgent. 
Prevents C++ emulator from randomizing inputs in unit testing.

Closes #44
 2016-05-20 16:31:12 -07:00
Ken McMillan
d69446e177 Add config classes to drive unit testing of L2 TileLink agents. 
Closes #43
 2016-05-20 16:15:43 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Howard Mao
4f84d8f757 make sure to hook up finish in ClientTileLinkEnqueuer 2016-05-18 13:13:34 -07:00
Colin Schmidt
abb0e2921b return non-zero exit codes when an assertion fires 
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
 2016-05-18 12:57:58 -07:00
Colin Schmidt
b396c68577 bump torture for priv-1.9 test-env 2016-05-17 22:02:38 -07:00
Colin Schmidt
b0ae003981 add firrtl to regression makefile 
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
 2016-05-17 17:34:20 -07:00
Andrew Waterman
684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Howard Mao
f138819992 fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00
Andrew Waterman
6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Christopher Celio
3fe00ce32a Update README.md 
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
 2016-05-10 22:12:02 -07:00
Andrew Waterman
533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
Andrew Waterman
fbff46d27d bump rocket 2016-05-10 10:57:03 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Andrew Waterman
e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
14a6e470c9 transform ids in TL -> NASTI converter if necessary 2016-05-07 21:19:27 -07:00
Howard Mao
3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao
1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala 2016-05-06 11:31:22 -07:00
Howard Mao
77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00