Howard Mao
|
1679cf4764
|
fix groundtest tilelink xacts
|
2016-06-09 15:42:44 -07:00 |
|
Megan Wachs
|
cee0cf345e
|
[debug] Update Debug ROM contents to write F..F to RAM in case of exception
|
2016-06-09 14:05:30 -07:00 |
|
Wesley W. Terpstra
|
a1ebc73477
|
tilelink: don't accidentally make a malformed union
Closes #55
|
2016-06-09 10:44:00 -07:00 |
|
Wesley W. Terpstra
|
31b72625aa
|
ahb: allow no-ops to progress also when a slave is !hready
|
2016-06-09 10:41:12 -07:00 |
|
Wesley W. Terpstra
|
7014eef339
|
ahb: fix bugs found using comparatortest
|
2016-06-09 10:41:11 -07:00 |
|
Andrew Waterman
|
9e86b9efc9
|
Add provisional breakpoint support
|
2016-06-08 22:34:19 -07:00 |
|
Scott Johnson
|
73ed4ea07b
|
grammar
English major I'm not, but my sister was and she says 'who' is correct here
|
2016-06-08 22:34:14 -07:00 |
|
mwachs5
|
93c1b17b52
|
[debug] Remove erroneous buffer on SB read data (#56)
|
2016-06-08 23:31:13 -04:00 |
|
Howard Mao
|
65b62a9e5f
|
unbreak the emulator
|
2016-06-08 15:38:39 -07:00 |
|
Howard Mao
|
40ab0a7960
|
fix TL width adapter and make it easier to switch inner data width
|
2016-06-08 15:38:39 -07:00 |
|
Howard Mao
|
a809a1712a
|
make sure clocks and reset signals get intialized properly
|
2016-06-08 15:38:39 -07:00 |
|
Albert Ou
|
5151570894
|
Fix valid signal for multibeat grants
|
2016-06-08 15:13:39 -07:00 |
|
Howard Mao
|
f421e2ab11
|
fix TileLinkWidthAdapter
|
2016-06-08 09:58:23 -07:00 |
|
Donggyu Kim
|
99b257316e
|
replace emulator with verilator for chisel3
|
2016-06-08 02:43:54 -07:00 |
|
Howard Mao
|
08e53a00f0
|
bump cde for better match failure stack trace
|
2016-06-07 16:15:10 -07:00 |
|
Howard Mao
|
2cd897e240
|
Revert "include the unmatched field in CDEMatchError"
This reverts commit ff2937a788.
|
2016-06-07 16:13:01 -07:00 |
|
Wesley W. Terpstra
|
324cabc494
|
tilelink: wmask was double the width it should be
When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
|
2016-06-07 14:04:01 -07:00 |
|
Howard Mao
|
8db27a36c4
|
fix Tile reset power on behavior
|
2016-06-07 11:06:38 -07:00 |
|
Palmer Dabbelt
|
e6c4372332
|
Fix "make run-asm-tests" for Chisel 3
This was just a missing Makefrag-verilog dependency (the .d file).
|
2016-06-06 21:36:55 -07:00 |
|
Andrew Waterman
|
2c17f828b6
|
bump chisel and rocket
|
2016-06-06 21:36:51 -07:00 |
|
Wesley W. Terpstra
|
5495705acf
|
Configs: enable AHB for FPGAs
|
2016-06-06 21:36:09 -07:00 |
|
Wesley W. Terpstra
|
ef27cc3a33
|
RocketChip: handle atomics only if needed
|
2016-06-06 21:36:03 -07:00 |
|
Wesley W. Terpstra
|
3e0ec855cf
|
RocketChip: add ahb mem interface
|
2016-06-06 21:35:59 -07:00 |
|
Wesley W. Terpstra
|
d2b505f2d2
|
RocketChip: rename mem to mem_axi in preparation for new bus type
|
2016-06-06 21:35:55 -07:00 |
|
Wesley W. Terpstra
|
2086c0d603
|
Configs: add a parameter to control the memory subsystem interface
|
2016-06-06 21:35:43 -07:00 |
|
Wesley W. Terpstra
|
2ddada1732
|
ahb: add mmio_ahb option
|
2016-06-06 21:35:39 -07:00 |
|
Wesley W. Terpstra
|
31f1dcaf84
|
ahb: rename mmio outputs to mmio_axi
|
2016-06-06 21:35:34 -07:00 |
|
Wesley W. Terpstra
|
7a24527448
|
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
|
2016-06-06 21:35:30 -07:00 |
|
Wesley W. Terpstra
|
f3a557b67b
|
ahb: AHB parameters should be site specific
Conflicts:
src/main/scala/Configs.scala
|
2016-06-06 21:35:24 -07:00 |
|
Howard Mao
|
172c4f25f4
|
bump groundtest and uncore
|
2016-06-06 17:45:30 -07:00 |
|
Howard Mao
|
ff2937a788
|
include the unmatched field in CDEMatchError
|
2016-06-06 11:23:20 -07:00 |
|
Howard Mao
|
2d66ac93d3
|
make sure HastiRAM cuts off the correct number of bits for word address
|
2016-06-06 09:26:51 -07:00 |
|
Andrew Waterman
|
d24c87f8ba
|
Update PLIC/PRCI address map (#124)
|
2016-06-06 04:51:55 -07:00 |
|
Andrew Waterman
|
dd85f2410f
|
Avoid need for cloneType
|
2016-06-05 23:47:56 -07:00 |
|
Andrew Waterman
|
631e3e2dd9
|
Make PRCI a singleton, not per-tile
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
|
2016-06-05 23:06:21 -07:00 |
|
Andrew Waterman
|
be7500e4a9
|
Update PLIC addr map
|
2016-06-05 23:04:51 -07:00 |
|
Megan Wachs
|
b832689642
|
Correct Debug ROM contents
|
2016-06-05 19:35:25 -07:00 |
|
Megan Wachs
|
605fb5b92f
|
[debug]: fix issue with subword select logic
|
2016-06-05 19:31:07 -07:00 |
|
Megan Wachs
|
3e8322816b
|
Correct DMINFO Fields
|
2016-06-05 19:29:50 -07:00 |
|
Megan Wachs
|
7e550ab07c
|
[debug] rocket: fix for issue 121, correct debug ROM and stall logic
|
2016-06-05 19:29:44 -07:00 |
|
Andrew Waterman
|
ece3ab9c3d
|
Refactor AddrMap and its usage (#122)
|
2016-06-03 17:29:05 -07:00 |
|
Andrew Waterman
|
2e88ffc364
|
Cope with changes to AddrMap
|
2016-06-03 13:48:09 -07:00 |
|
Andrew Waterman
|
f1745bf142
|
Allow PLIC nPriorities=0 (priority fixed at 1)
|
2016-06-02 13:48:29 -07:00 |
|
Andrew Waterman
|
b7ca2145b3
|
Fix PLIC control bug when !grant.ready
|
2016-06-02 13:47:59 -07:00 |
|
Andrew Waterman
|
c8338ad809
|
Instantiate Debug Module (#119)
|
2016-06-02 10:53:41 -07:00 |
|
Andrew Waterman
|
0866b4c045
|
Can't assign to Vec literals
|
2016-06-01 23:36:34 -07:00 |
|
Andrew Waterman
|
20e1de08da
|
Avoid chisel2 pitfall
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
|
2016-06-01 23:35:49 -07:00 |
|
Andrew Waterman
|
5629fb62bf
|
Avoid bitwise sub-assignment
|
2016-06-01 21:59:02 -07:00 |
|
Andrew Waterman
|
9518b3d589
|
Fix arithmetic in ROM row count
|
2016-06-01 21:59:02 -07:00 |
|
Andrew Waterman
|
8e80d1ec80
|
Avoid floating-point arithmetic where integers suffice
|
2016-06-01 21:59:02 -07:00 |
|