a78e28523c
Chisel3: Don't mix Mux types
2015-07-11 14:06:08 -07:00
3233867390
Use Chisel3 SeqMem construct
2015-07-11 13:34:57 -07:00
5ed2899e56
Merge pull request #10 from wsong83/fix
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L1 D$ writeback unit, reduce re-read data array
2015-07-06 15:18:49 -07:00
5362e2bbbd
New machine-mode timer facility
2015-07-05 16:38:49 -07:00
5e009ecc75
Fix an apparently benign PC sign-extension bug
2015-06-11 16:08:39 -07:00
4db60d9e9d
code clean in dcache, no need to check the condition twice.
2015-06-02 22:06:12 +01:00
b6e68773fd
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
2015-05-30 16:25:27 +01:00
6a9390c50e
Avoid spurious D$ assertion failures
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For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
b09832f1b5
ICache now returns the "next PC" signal.
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useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
4d6ebded02
Added assert to nbdcache
2015-04-11 02:58:34 -07:00
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
8fc2d38ca9
Removed unnecessary signal in CSRIO
2015-04-11 02:20:34 -07:00
2f88c5ca9d
Renamed PCR to CSR
2015-04-11 02:16:44 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
9ade0e41cc
Integrate divide/sqrt unit
2015-04-04 16:39:17 -07:00
fe27b9b1b2
Support writing sstatus.fs even without an FPU
2015-04-04 15:20:18 -07:00
bce62d5774
Update PTE format to reflect reserved bits
2015-04-04 15:19:15 -07:00
d912ea265e
New virtual memory implementation (Sv39)
2015-03-27 16:20:59 -07:00
faada5f110
Mask off LSBs of sepc/mepc/stvec
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Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
2015-03-25 00:20:58 -07:00
543ac91cf2
Misaligned fetches can't happen at the I$ anymore
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They are caught before the I$ ever sees them, so leverage that fact.
2015-03-24 23:55:43 -07:00
90b31586ff
Misc. CSR fixes/improvements
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- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
2015-03-24 23:50:18 -07:00
822698b567
support disabling supervisor mode (via UseVM parameter)
2015-03-24 19:32:45 -07:00
0332c1e7fe
Reduce latency of page table walks
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A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
2015-03-24 18:58:38 -07:00
31d17cbf86
Hard-wire LSB of JALR to 0, as sent to BTB
2015-03-21 00:16:34 -07:00
53617d6df5
fix long-standing dcache bug
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have to initialize register, if it is used the same cycle it is begin written
2015-03-17 21:45:17 -07:00
5b4653b621
fix rocc exception/s bit
2015-03-17 05:08:23 -07:00
66388be1ce
Merge [shm]call into ecall, [shm]ret into eret
2015-03-17 02:24:41 -07:00
2c875555a2
Separate exception return control from exception control
2015-03-17 00:14:32 -07:00
e85c54cc4b
New privileged ISA implementation
2015-03-14 02:49:07 -07:00
ebbd14254c
uncached port should be a HeaderlessUncachedTileLinkIO type
2015-03-13 02:12:23 -07:00
51e4cd7616
Added UncachedTileLinkIO port to RocketTile, simplify arbitration
2015-03-12 16:30:04 -07:00
ea018b3d84
stall rocket decode when not rocc ready
2015-03-11 22:33:03 -07:00
e293d89035
fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
2015-03-10 10:28:05 -07:00
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
b36d751250
sret bugfix: bypass arbiter
2015-03-05 13:14:16 -08:00
06dea3790a
Removed sret from ptw; sret now comes thru io.cpu to dcache
2015-03-03 16:50:41 -08:00
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
0b131173e6
WritebackUnit multibeat control logic bugfix
2015-02-16 10:59:57 -08:00
aa46b8b72d
Slightly refactor TLBResp
2015-02-03 19:32:37 -08:00
3d35ccd401
Explicitely convert results of Bits Muxes to UInt
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Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
