 Yunsup Lee
|
a2381d2faf
|
RoCC PTW refactoring
|
2016-02-25 17:26:42 -08:00 |
|
|
Yunsup Lee
|
15ac4d317f
|
RoCC PTW refactoring
|
2016-02-25 17:15:38 -08:00 |
|
|
Yunsup Lee
|
ea8ba49805
|
improve memory system: specialize MultiChannel routing
|
2015-11-18 21:58:22 -08:00 |
|
|
Yunsup Lee
|
94d2dd3053
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-16 23:29:25 -08:00 |
|
|
Yunsup Lee
|
5e2698adbc
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-14 16:44:55 -08:00 |
|
|
Yunsup Lee
|
8916c7e99c
|
push rocket
|
2015-11-14 16:43:28 -08:00 |
|
|
Yunsup Lee
|
213c1a4c81
|
fix fdiv/fsqrt control bug in fpu
|
2015-11-14 16:43:15 -08:00 |
|
|
Yunsup Lee
|
4dd097d156
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-14 14:52:13 -08:00 |
|
|
Yunsup Lee
|
6a6371fdb6
|
move to new version of hardfloat
|
2015-11-14 14:50:13 -08:00 |
|
|
Yunsup Lee
|
3c3c946755
|
move to new version of hardfloat
|
2015-11-14 14:49:17 -08:00 |
|
|
Yunsup Lee
|
608e4b2851
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-12 20:44:25 -08:00 |
|
|
Yunsup Lee
|
df5daaa72e
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-06 23:57:42 -08:00 |
|
|
Yunsup Lee
|
1e772daeea
|
no spaces in Makefrag
|
2015-11-05 16:42:05 -08:00 |
|
 Yunsup LeeandHoward Mao
|
51116e0674
|
add 2 and 4 memory channel configs
|
2015-11-05 10:48:32 -08:00 |
|
|
Yunsup LeeandHoward Mao
|
0d245741bc
|
add multichannel NASTI support in Verilog testbench
|
2015-11-05 10:48:32 -08:00 |
|
|
Yunsup Lee
|
a175afae73
|
make ZscaleChip work with new parameters framework
|
2015-10-25 10:24:39 -07:00 |
|
|
Yunsup Lee
|
c7235fecb5
|
further state optimization in CSRfile when not UseVM
|
2015-10-25 10:23:46 -07:00 |
|
|
Yunsup Lee
|
cedef98045
|
fix NASTI -> MemIO converter bug
|
2015-10-19 21:43:59 -07:00 |
|
|
Yunsup Lee
|
efd6458a3d
|
add zscale programs
|
2015-07-27 19:06:06 -07:00 |
|
|
Yunsup Lee
|
e571ebaf7f
|
bump zscale
|
2015-07-27 17:23:38 -07:00 |
|
|
Yunsup Lee
|
caf89baeb7
|
update zscale
|
2015-07-23 13:59:45 -07:00 |
|
|
Yunsup Lee
|
a99b1e3a01
|
append config name to generated Makefrag filename
|
2015-07-17 12:34:49 -07:00 |
|
|
Yunsup Lee
|
777facf91e
|
update tools
|
2015-07-17 12:33:19 -07:00 |
|
|
Yunsup Lee
|
e7802825c3
|
add Zscale testing
|
2015-07-17 12:02:02 -07:00 |
|
|
Yunsup Lee
|
4c7c3f5bb2
|
add test generate for ZscaleTop
|
2015-07-14 16:26:28 -07:00 |
|
|
Yunsup Lee
|
d6df479870
|
move 'include /Makefrag' out of top-level Makefrag
|
2015-07-14 16:13:32 -07:00 |
|
|
Yunsup Lee
|
09e29e8fe0
|
add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
|
2015-07-07 20:38:47 -07:00 |
|
|
Yunsup Lee
|
e6a13cdeba
|
New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
|
2015-07-07 17:26:07 -07:00 |
|
|
Yunsup Lee
|
b9fb1bb46e
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-04-29 00:43:53 -07:00 |
|
|
Yunsup Lee
|
aa5435800d
|
fix get merging, and always turn it on
|
2015-03-17 22:43:00 -07:00 |
|
|
Yunsup Lee
|
53617d6df5
|
fix long-standing dcache bug
have to initialize register, if it is used the same cycle it is begin written
|
2015-03-17 21:45:17 -07:00 |
|
|
Yunsup Lee
|
f4f59464df
|
fix pending_puts initialization
|
2015-03-17 21:44:26 -07:00 |
|
|
Yunsup Lee
|
9de5161d7a
|
guard all writes to data ram with masks
|
2015-03-17 20:24:04 -07:00 |
|
|
Yunsup Lee
|
d14efce0b4
|
fix wmask_buffer initialization
|
2015-03-17 19:54:11 -07:00 |
|
|
Yunsup Lee
|
2d7375760d
|
set pending_writes for puts
|
2015-03-17 18:35:04 -07:00 |
|
|
Yunsup Lee
|
504eedbf89
|
fixes in in bit manipulation
|
2015-03-17 18:07:52 -07:00 |
|
|
Yunsup Lee
|
4fd01d82b8
|
don't block finish messages when grant'ing
|
2015-03-17 17:48:02 -07:00 |
|
|
Yunsup Lee
|
a52a729ab9
|
bugfix wmask handling
|
2015-03-17 15:54:21 -07:00 |
|
 Yunsup LeeandHenry Cook
|
0e51fef200
|
bugfix where an in-progress acquire can be blocked by another acquire tracker being free'd up in between
|
2015-03-17 05:37:56 -07:00 |
|
|
Yunsup Lee
|
5b4653b621
|
fix rocc exception/s bit
|
2015-03-17 05:08:23 -07:00 |
|
|
Yunsup Lee
|
145e15701e
|
bugfix where an in-progress acquire can be blocked by another acquire tracker being free'd up in between
|
2015-03-16 18:47:16 -07:00 |
|
|
Yunsup Lee
|
ebbd14254c
|
uncached port should be a HeaderlessUncachedTileLinkIO type
|
2015-03-13 02:12:23 -07:00 |
|
|
Yunsup Lee
|
3a78ca210d
|
bugfix in uncached TL to TL convertors
|
2015-03-12 16:33:41 -07:00 |
|
|
Yunsup Lee
|
2c31ed6426
|
previous bug fix for meta data writeback wasn't quite right
|
2015-03-12 15:34:20 -07:00 |
|
|
Yunsup Lee
|
5e40c8ba77
|
write back meta data when cache miss even when coherence meta data is clean
|
2015-03-12 14:36:46 -07:00 |
|
|
Yunsup Lee
|
ea018b3d84
|
stall rocket decode when not rocc ready
|
2015-03-11 22:33:03 -07:00 |
|
|
Yunsup Lee
|
3ab1aca7de
|
L2 subblock access bugfix
|
2015-03-11 01:56:47 -07:00 |
|
|
Yunsup Lee
|
4f57985198
|
change organization to riscv
|
2015-02-17 14:43:11 -08:00 |
|
|
Yunsup Lee
|
170f1fecbc
|
push chisel,rocket,riscv-tools
|
2014-10-21 12:32:58 -07:00 |
|
|
Yunsup Lee
|
f15baeea49
|
fix markdown for webpage
|
2014-10-07 03:55:00 -07:00 |
|
|
Yunsup Lee
|
5ca7f08226
|
change rocket submodule
|
2014-10-07 03:19:48 -07:00 |
|
|
Yunsup Lee
|
e1b8f69cb5
|
change submodule pointers to https
|
2014-10-07 03:16:20 -07:00 |
|
|
Yunsup Lee
|
447761b06c
|
fix typo in README
|
2014-10-07 02:09:34 -07:00 |
|
|
Yunsup Lee
|
91f211f766
|
updates to README
|
2014-10-07 02:08:03 -07:00 |
|
|
Yunsup Lee
|
702ddabe26
|
add ExampleSmallConfig for README
|
2014-10-07 02:07:59 -07:00 |
|
|
Yunsup Lee
|
ae9b78d9ef
|
add what/how explanation to README
|
2014-10-07 02:07:39 -07:00 |
|
|
Yunsup Lee
|
e25d420155
|
Improve ChiselConfig composability; bump chisel
|
2014-10-06 13:43:40 -07:00 |
|
|
Yunsup Lee
|
73eac94a65
|
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
|
2014-10-06 13:40:35 -07:00 |
|
|
Yunsup Lee
|
6c18cd9559
|
add new fpga-zynq as submodule
|
2014-09-30 09:32:02 -07:00 |
|
|
Yunsup Lee
|
7a28d2b47c
|
forgot to move more hwacha stuff out in rocket-chip
|
2014-09-25 15:34:18 -07:00 |
|
|
Yunsup Lee
|
70b0f9fd4d
|
error out for PCWM-L, port width mismatch
|
2014-09-25 06:50:50 -07:00 |
|
|
Yunsup Lee
|
e2ed81dcd2
|
push chisel
|
2014-09-25 06:50:05 -07:00 |
|
|
Yunsup Lee
|
3b9624277a
|
normalize rocket-chip to reference-chip
|
2014-09-25 06:45:09 -07:00 |
|
|
Yunsup Lee
|
6495d0e6f7
|
bump rocket,uncore
|
2014-09-17 11:26:12 -07:00 |
|
|
Yunsup Lee
|
f249da1803
|
update README
|
2014-09-17 11:25:14 -07:00 |
|
|
Yunsup Lee
|
238f7761f6
|
update README
|
2014-09-17 11:23:25 -07:00 |
|
|
Yunsup Lee
|
041a362943
|
push chisel
|
2014-09-17 11:12:12 -07:00 |
|
|
Yunsup Lee
|
221007595b
|
allow BACKEND/CONFIG be environment variables
|
2014-09-17 11:12:08 -07:00 |
|
|
Yunsup Lee
|
ef2e96211c
|
bump chisel/hardfloat/rocket/uncore
|
2014-09-12 18:10:00 -07:00 |
|
|
Yunsup Lee
|
09de2e2794
|
compute number of outstanding misses for DRAMSideLLCNull
|
2014-09-12 18:09:38 -07:00 |
|
|
Yunsup Lee
|
8abf62fae3
|
add LICENSE
|
2014-09-12 18:06:41 -07:00 |
|
|
Yunsup Lee
|
25180b71f7
|
add LICENSE
|
2014-09-12 15:36:42 -07:00 |
|
|
Yunsup Lee
|
49b027db2c
|
forgot to add LICENSE file
|
2014-09-12 15:36:29 -07:00 |
|
|
Yunsup Lee
|
0b51d70bd2
|
add LICENSE
|
2014-09-12 15:31:38 -07:00 |
|
|
Yunsup Lee
|
e40a6fdd64
|
more tweaks to README
|
2014-09-12 10:22:00 -07:00 |
|
|
Yunsup Lee
|
c57dea415c
|
fix markdown
|
2014-09-12 10:18:14 -07:00 |
|
|
Yunsup Lee
|
1cfd9f5a0e
|
add LICENSE
|
2014-09-12 10:15:04 -07:00 |
|
|
Yunsup Lee
|
2c33852c52
|
final touches
|
2014-09-12 00:19:29 -07:00 |
|
|
Yunsup Lee
|
275b72368b
|
add CONFIG to the name of simulator executable
|
2014-09-11 22:11:58 -07:00 |
|
|
Yunsup Lee
|
c98afa1fea
|
turn off DRAMSideLLC
|
2014-09-11 22:10:25 -07:00 |
|
|
Yunsup Lee
|
b5a64487eb
|
turn off DRAMSideLLC
|
2014-09-11 22:07:44 -07:00 |
|
|
Yunsup Lee
|
f8d450b4e2
|
mark DRAMSideLLC as HasKnownBug
|
2014-09-11 22:06:03 -07:00 |
|
|
Yunsup Lee
|
9dfaf5459e
|
bump hardfloat,riscv-tools
|
2014-09-11 03:08:21 -07:00 |
|
|
Yunsup Lee
|
5f8bd18fac
|
Makefiles should be perfect
|
2014-09-11 02:53:46 -07:00 |
|
|
Yunsup Lee
|
bb22ecc8b5
|
fix rocket interrupt issue
h/t Andrew
|
2014-09-11 02:52:05 -07:00 |
|
|
Yunsup Lee
|
086bb02c24
|
check RISCV envirnoment variable
|
2014-09-11 02:38:21 -07:00 |
|
|
Yunsup Lee
|
02c08a156f
|
generate consts.vh from chisel source
|
2014-09-10 17:14:55 -07:00 |
|
|
Yunsup Lee
|
cfecd8832d
|
tease out reference-chip specific stuff
|
2014-09-09 20:49:28 -07:00 |
|
|
Yunsup Lee
|
6b6bdd2b83
|
decommission Slave top-level module for fpga build
|
2014-09-08 00:23:15 -07:00 |
|
|
Yunsup Lee
|
ddfd3ce968
|
further generalize fpga/vlsi builds
|
2014-09-08 00:21:57 -07:00 |
|
|
Yunsup Lee
|
3175a40509
|
add berkeley-hardfloat as submodule
|
2014-09-08 00:18:49 -07:00 |
|
|
Yunsup Lee
|
1e5b2f658f
|
remove existing hardfloat repository
|
2014-09-07 23:45:47 -07:00 |
|
|
Yunsup Lee
|
1cb2d1d7b7
|
initialize all SRAMs to avoid X propagation problem
|
2014-09-04 11:06:01 -07:00 |
|
|
Yunsup Lee
|
763c57931b
|
fix problem introduced with verilog generation in vsim/fsim
|
2014-09-04 09:49:57 -07:00 |
|
|
Yunsup Lee
|
7734285507
|
forgot to comment out hwacha
|
2014-09-01 09:01:36 -07:00 |
|
|
Yunsup Lee
|
0d18e491c7
|
update gitignore
|
2014-09-01 08:59:59 -07:00 |
|
|
Yunsup Lee
|
882fecf43a
|
update README
|
2014-08-31 20:57:16 -07:00 |
|
|
Yunsup Lee
|
c03c09ec31
|
update for rocket-chip release
|
2014-08-31 20:26:55 -07:00 |
|
|
Yunsup Lee
|
4ac8e59b1f
|
add .gitignore
|
2014-08-18 19:27:50 -07:00 |
|
|
Yunsup Lee
|
d520846638
|
add README and sbt files
|
2014-08-18 19:23:10 -07:00 |
|