riscv/rocket-chip
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initialize all SRAMs to avoid X propagation problem

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This commit is contained in:
Yunsup Lee 2014-09-04 11:06:01 -07:00
parent 763c57931b
commit 1cb2d1d7b7
2 changed files with 16 additions and 0 deletions
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8
fsim/fpga_mem_gen
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@ -122,6 +122,14 @@ def gen_mem(name, width, depth, ports, mask_gran):
sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
decl += ['reg [%d:0] ram [%d:0];' % (width-1, depth-1)]
decl += ['`ifndef SYNTHESIS']
decl += [' integer initvar;']
decl += [' initial begin']
decl += [' #0.002;']
decl += [' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth]
decl += [' ram[initvar] = {%d {$random}};' % ((width-1)/32+1)]
decl += [' end']
decl += ['`endif']
for pid in readports:
decl += ['reg [%d:0] reg_R%dA;' % (addr_width-1, pid)]

8
vsim/vlsi_mem_gen
View File

@ -55,6 +55,14 @@ def gen_mem(name, width, depth, ports):
tup = (depth, width, nr, nw, nrw, masked)
decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
decl.append('`ifndef SYNTHESIS')
decl.append(' integer initvar;')
decl.append(' initial begin')
decl.append(' #0.002;')
decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
decl.append(' end')
decl.append('`endif')
for pid in readports:
decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))