Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
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Yunsup Lee
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f97a801d60
commit
73eac94a65
@ -8,113 +8,121 @@ import rocket._
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import rocket.Util._
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class DefaultConfig extends ChiselConfig {
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type PF = PartialFunction[Any,Any]
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val topDefinitions:World.TopDefs = {
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(pname,site,here) => pname match {
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//RocketChip Parameters
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case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)}
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => Dump("MEM_TAG_BITS", 5)
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
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//Params used by all caches
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case ECCCode => None
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case WordBits => site(XprLen)
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case Replacer => () => new RandomReplacement(site(NWays))
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case BlockOffBits => site(CacheName) match {
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case "L1I" | "L1D" => log2Up(site(TLDataBits)/8)
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case "L2" => 0
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(pname,site,here) => {
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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pname match {
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//RocketChip Parameters
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case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)}
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => Dump("MEM_TAG_BITS", 5)
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case BlockOffBits => findBy(CacheName)
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case ECCCode => None
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case WordBits => site(XprLen)
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case Replacer => () => new RandomReplacement(site(NWays))
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//Cache-Specific Params
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case "L1I" => {
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case NSets => 128
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case NWays => 2
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case RowBits => 4*site(CoreInstBits)
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case BlockOffBits => log2Up(site(TLDataBits)/8)
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //128
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => 2*site(CoreDataBits)
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case BlockOffBits => log2Up(site(TLDataBits)/8)
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}:PF
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case "L2" => {
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case NSets => 512
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case NWays => 8
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case RowBits => site(TLDataBits)
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case BlockOffBits => 0
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}:PF
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//L1InstCache
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case NITLBEntries => 8
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case NBTBEntries => 62
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case NRAS => 2
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//L1DataCache
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case NDTLBEntries => 8
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2CacheParams
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case NReleaseTransactors => Knob("L2_REL_XACTS")
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case NAcquireTransactors => Knob("L2_ACQ_XACTS")
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case NClients => site(NTiles) + 1
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//Tile Constants
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
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//Rocket Core Constants
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XprLen => 64
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case NMultXpr => 32
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case BuildFPU => Some(() => Module(new FPU))
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XprLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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//Uncore Paramters
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case LNMasters => site(NBanks)
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case LNClients => site(NTiles)+1
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case LNEndpoints => site(LNMasters) + site(LNClients)
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case TLId => "inner"
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case TLCoherence => site(Coherence)
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case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLMasterXactIdBits => site(TLId) match {
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case "inner" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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case "outer" => 1
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}
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case TLClientXactIdBits => site(TLId) match {
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case "inner" => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
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case "outer" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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}
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case TLDataBits => site(CacheBlockBytes)*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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case NTiles => Knob("NTILES")
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case NBanks => Knob("NBANKS")
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case NOutstandingMemReqs => 16 //site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
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case BankIdLSB => 5
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => true
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case BuildCoherenceMaster => (id: Int) => {
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Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
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}
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case Coherence => new MSICoherence(() => new NullRepresentation)
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}
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case NSets => site(CacheName) match {
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case "L1I" => 128
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case "L1D" => Knob("L1D_SETS") //128
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case "L2" => 512
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}
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case NWays => site(CacheName) match {
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case "L1I" => 2
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case "L1D" => Knob("L1D_WAYS") //4
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case "L2" => 8
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}
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case RowBits => site(CacheName) match {
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case "L1I" => 4*site(CoreInstBits)
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case "L1D" => 2*site(CoreDataBits)
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case "L2" => site(TLDataBits)
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}
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//L1InstCache
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case NITLBEntries => 8
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case NBTBEntries => 62
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case NRAS => 2
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//L1DataCache
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case NDTLBEntries => 8
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2CacheParams
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case NReleaseTransactors => Knob("L2_REL_XACTS")
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case NAcquireTransactors => Knob("L2_ACQ_XACTS")
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case NClients => site(NTiles) + 1
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//Tile Constants
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
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//Rocket Core Constants
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XprLen => 64
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case NMultXpr => 32
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case BuildFPU => Some(() => Module(new FPU))
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XprLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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//Uncore Paramters
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case LNMasters => site(NBanks)
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case LNClients => site(NTiles)+1
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case LNEndpoints => site(LNMasters) + site(LNClients)
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case TLId => "inner"
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case TLCoherence => site(Coherence)
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case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLMasterXactIdBits => site(TLId) match {
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case "inner" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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case "outer" => 1
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}
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case TLClientXactIdBits => site(TLId) match {
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case "inner" => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
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case "outer" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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}
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case TLDataBits => site(CacheBlockBytes)*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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case NTiles => Knob("NTILES")
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case NBanks => Knob("NBANKS")
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case NOutstandingMemReqs => 16 //site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
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case BankIdLSB => 5
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => true
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case BuildCoherenceMaster => (id: Int) => {
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Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
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}
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case Coherence => new MSICoherence(() => new NullRepresentation)
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}
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}
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override val knobValues:Any=>Any = {
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