further generalize fpga/vlsi builds

Makefrag

@@ -1,5 +1,4 @@
 MODEL := Top
-FPGAMODEL := FPGATop
 CXX := g++
 CXXFLAGS := -O1
 
@@ -22,23 +21,14 @@ timeout_cycles = 100000000
 
 # VLSI Backend
 $(generated_dir)/$(MODEL).v: $(chisel_srcs)
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend rocketchip.RocketChipBackend --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.DefaultVLSIConfig"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG)"
 	cd $(generated_dir) && \
 	if [ -a $(MODEL).conf ]; then \
-		sed -i 's*^*$(vlsi_mem_gen) *' $(MODEL).conf && \
-		sed -i 's*$$* >> $(MODEL).v*' $(MODEL).conf && \
-		sh $(MODEL).conf; \
+	  $(mem_gen) $(generated_dir)/$(MODEL).conf >> $(generated_dir)/$(MODEL).v; \
 	fi
 
-# FPGA Backend
-$(generated_dir)/$(FPGAMODEL).v: $(chisel_srcs)
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(FPGAMODEL) --backend fpga --targetDir $(generated_dir) --configInstance rocketchip.DefaultFPGAConfig"
-
-$(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen)
-	$(mem_gen) $(generated_dir)/$(FPGAMODEL).conf > $(generated_dir)/$(FPGAMODEL)Mem.v
-
 $(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.DefaultVLSIConfig"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
 
 #--------------------------------------------------------------------
 # DRAMSim2

fsim/Makefile

@@ -15,6 +15,9 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
+BACKEND = fpga
+CONFIG = DefaultFPGAConfig
+
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim

fsim/Makefrag

@@ -6,8 +6,7 @@
 # Verilog sources
 
 sim_vsrcs = \
-	$(generated_dir)/$(FPGAMODEL).v \
-	$(generated_dir)/$(FPGAMODEL)Mem.v \
+	$(generated_dir)/$(MODEL).v \
 	$(generated_dir)/memdessertMemDessert.v \
 	$(base_dir)/vsrc/const.vh \
 	$(base_dir)/vsrc/rocketTestHarness.v \
@@ -45,7 +44,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
 	+define+FPGA \
-	+define+TOP=$(FPGAMODEL) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=rocketTestHarness.verbose \
 	+libext+.v \

src/main/scala/PublicConfigs.scala

@@ -160,6 +160,7 @@ class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
       case NITLBEntries => 4
       case NBTBEntries => 8
       case NDTLBEntries => 4
+      case UseBackupMemoryPort => false
       case _ => default.topDefinitions(pname,site,here)
     }
   }

vsim/Makefile

@@ -11,10 +11,13 @@ default: all
 
 base_dir = $(abspath ..)
 generated_dir = $(abspath ./generated-src)
-vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
+mem_gen = $(base_dir)/vsim/vlsi_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
+BACKEND = rocketchip.RocketChipBackend
+CONFIG = DefaultVLSIConfig
+
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim

vsim/Makefrag

@@ -43,7 +43,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
-	+define+TOP=$(MODEL) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=rocketTestHarness.verbose \
 	+libext+.v \

vsim/vlsi_mem_gen

@@ -4,6 +4,31 @@ import math
 
 use_latches = 0
 
+def parse_line(line):
+  name = ''
+  width = 0
+  depth = 0
+  ports = ''
+  mask_gran = 1
+  tokens = line.split()
+  i = 0
+  for i in xrange(0,len(tokens),2):
+    s = tokens[i]
+    if s == 'name':
+      name = tokens[i+1]
+    elif s == 'width':
+      width = int(tokens[i+1])
+    elif s == 'depth':
+      depth = int(tokens[i+1])
+    elif s == 'ports':
+      ports = tokens[i+1].split(',')
+    elif s == 'mask_gran':
+      # currently used only for fpga, but here for .conf format compatability
+      mask_gran = int(tokens[i+1])
+    else:
+      sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
+  return (name, width, depth, ports)
+
 def gen_mem(name, width, depth, ports):
   addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
   port_spec = ['input CLK', 'input RST', 'input init']
@@ -112,33 +137,11 @@ def gen_mem(name, width, depth, ports):
 endmodule\n" % (name, ',\n  '.join(port_spec), body)
   return s
 
-name = ''
-width = 0
-depth = 0
-ports = ''
+def main():
+  if len(sys.argv) < 2:
+    sys.exit('Please give a .conf file as input')
+  for line in open(sys.argv[1]):
+    print gen_mem(*parse_line(line))
 
-tokens = sys.argv[1:len(sys.argv)]
-i = 0
-while i < len(tokens):
-  a = tokens[i]
-  if a == 'name':
-    name = tokens[i+1]
-    i += 1
-  elif a == 'width':
-    width = int(tokens[i+1])
-    i += 1
-  elif a == 'depth':
-    depth = int(tokens[i+1])
-    i += 1
-  elif a == 'ports':
-    ports = tokens[i+1].split(',')
-    i += 1
-  elif a == 'mask_gran':
-    # currently used only for fpga, but here for .conf format compatability
-    mask_gran = int(tokens[i+1])
-    i += 1
-  else:
-    sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
-  i += 1
-
-print gen_mem(name, width, depth, ports)
+if __name__ == '__main__':
+  main()

vsrc/rocketTestHarness.v

@@ -112,7 +112,7 @@ module rocketTestHarness;
   wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
   wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
 
-  `TOP dut
+  Top dut
   (
     .clk(clk),
     .reset(reset),