Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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commit
94d2dd3053
@ -203,6 +203,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mtdeleg -> UInt(0),
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CSRs.mreset -> UInt(0),
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CSRs.mtvec -> UInt(MTVEC),
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CSRs.miobase -> UInt(p(junctions.MMIOBase)),
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CSRs.mipi -> UInt(0),
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CSRs.mip -> reg_mip.toBits,
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CSRs.mie -> reg_mie.toBits,
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CSRs.mscratch -> reg_mscratch,
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@ -211,7 +213,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mcause -> reg_mcause,
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CSRs.mtimecmp -> reg_mtimecmp,
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CSRs.mhartid -> io.host.id,
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CSRs.send_ipi -> io.host.id, /* don't care */
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CSRs.stats -> reg_stats,
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CSRs.mtohost -> reg_tohost,
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CSRs.mfromhost -> reg_fromhost)
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@ -353,9 +354,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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io.time := reg_cycle
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io.host.ipi_req.valid := cpu_wen && decoded_addr(CSRs.send_ipi)
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io.host.ipi_req.bits := io.rw.wdata
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io.csr_replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
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io.csr_replay := false
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io.csr_stall := reg_wfi
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when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
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@ -400,6 +399,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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reg_mip.msip := new_mip.msip
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}
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when (decoded_addr(CSRs.mipi)) {
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reg_mip.msip := true
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}
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when (decoded_addr(CSRs.mie)) {
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val new_mie = new MIP().fromBits(wdata)
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if (usingVM) {
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@ -449,9 +451,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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}
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io.host.ipi_rep.ready := true
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when (io.host.ipi_rep.valid) { reg_mip.msip := true }
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when(this.reset) {
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reg_mstatus.zero1 := 0
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reg_mstatus.zero2 := 0
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@ -299,7 +299,8 @@ object CSRs {
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val mtohost = 0x780
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val mfromhost = 0x781
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val mreset = 0x782
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val send_ipi = 0x783
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val mipi = 0x783
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val miobase = 0x784
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val cycleh = 0xc80
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val timeh = 0xc81
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val instreth = 0xc82
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@ -367,7 +368,8 @@ object CSRs {
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res += mtohost
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res += mfromhost
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res += mreset
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res += send_ipi
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res += mipi
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res += miobase
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res.toArray
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}
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val all32 = {
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